公开(公告)号：US08774544B1

公开(公告)日：2014-07-08

申请号：US12842745

申请日：2010-07-23

Applicant: Gabor Szedo ,  Jeffrey D. Stroomer ,  Jose R. Alvarez

Inventor： Gabor Szedo ,  Jeffrey D. Stroomer ,  Jose R. Alvarez

IPC: G06K9/40 ,  H04N5/21

CPC classification number: G06K9/40 ,  G06T5/002 ,  G06T5/50 ,  G06T2207/10016 ,  G06T2207/20012 ,  G06T2207/20182 ,  H04N5/21

Abstract: Circuits, systems, and methods for processing outlier pixels include a spatial filter and a temporal filter. The spatial filter is configured to compute a pixel difference for each pixel as a function of a pixel value of the pixel and pixel values of nearby pixels within each frame. The spatial filter is configured to dynamically add the pixel to a candidate list when the pixel difference exceeds a threshold value. The temporal filter dynamically removes a pixel from the candidate list when there is a divergence of a pixel value of the pixel in successive frames. The temporal filter determines a pixel in the candidate list is an outlier pixel when there is no such divergence in the successive frames.

Abstract translation: 用于处理异常值像素的电路，系统和方法包括空间滤波器和时间滤波器。 空间滤波器被配置为根据像素的像素值和每帧内的附近像素的像素值来计算每个像素的像素差。 空间滤波器被配置为当像素差异超过阈值时，将像素动态地添加到候选列表。 当连续帧中的像素的像素值发散时，时间滤波器从候选列表中动态地去除像素。 当连续帧中没有这样的发散时，时间滤波器确定候选列表中的像素是异常值像素。

公开(公告)号：US08441562B1

公开(公告)日：2013-05-14

申请号：US12875077

申请日：2010-09-02

Applicant: Gabor Szedo ,  Jose R. Alvarez

Inventor： Gabor Szedo ,  Jose R. Alvarez

IPC: H04N5/335

CPC classification number: H04N17/002 ,  H04N9/045

Abstract: In one embodiment of the present invention, a method for determining a phase alignment of a Bayer color filter array is provided. A quincunx lattice of the color filter array corresponding to a first color component is determined from an input frame of image data. Elements of the color filter array corresponding to first and second rectangular lattices of the color filter array are selected. Second and third color components corresponding to elements of the first and second rectangular lattices are determined from the sample values in an input frame of image data.

Abstract translation: 在本发明的一个实施例中，提供了一种用于确定拜耳滤色器阵列的相位对准的方法。 从图像数据的输入帧确定与第一颜色分量相对应的滤色器阵列的五点阵。 选择与滤色器阵列的第一和第二矩形格子相对应的滤色器阵列的元件。 从图像数据的输入帧中的样本值确定与第一和第二矩形格子的元素对应的第二和第三颜色成分。

公开(公告)号：US08400533B1

公开(公告)日：2013-03-19

申请号：US12710866

申请日：2010-02-23

Applicant: Gabor Szedo ,  Jose R. Alvarez

Inventor： Gabor Szedo ,  Jose R. Alvarez

IPC: H04N5/217 ,  H04N9/64 ,  H04N9/68 ,  H04N5/228

CPC classification number: H04N9/045 ,  H04N5/217 ,  H04N9/646

Abstract: A method of reducing aberrations in a digital image comprises capturing input samples associated with a plurality of pixels arranged in a matrix, wherein each pixel is associated with a color defining the digital image; establishing vertical chrominance groups associated with columns of the matrix and horizontal chrominance groups associated with rows of the matrix; determining chrominance values for the chrominance groups; determining, for each chrominance group, a mean value and, a sum of absolute differences between the chrominance values and the mean value for the chrominance values of the chrominance group; calculating, by a signal processing device, a plurality of weights comprising vertical weights associated with the vertical chrominance groups and horizontal weights associated with the horizontal chrominance groups based upon the sums of absolute differences; and determining a missing color component for a predetermined pixel of the plurality of pixels using the plurality of weights.

Abstract translation: 减少数字图像中的像差的方法包括捕获与排列成矩阵的多个像素相关联的输入样本，其中每个像素与定义数字图像的颜色相关联; 建立与矩阵的列相关联的垂直色度组和与矩阵的行相关联的水平色度组; 确定色度组的色度值; 对于每个色度组，确定色度值的色度值和色度值的色度值的平均值之间的平均值和绝对差之和; 由信号处理装置根据绝对差的和计算包括与垂直色度组相关联的垂直权重和与水平色度组相关联的水平权重的多个权重; 以及使用所述多个权重来确定所述多个像素中的预定像素的缺失颜色分量。

公开(公告)号：US08181149B1

公开(公告)日：2012-05-15

申请号：US12553726

申请日：2009-09-03

Applicant: Sean A. Kelly ,  Gabor Szedo

Inventor： Sean A. Kelly ,  Gabor Szedo

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: Approaches for assembling an electronic circuit design. A processor performs operations including instantiating and coupling a plurality of instances of functional blocks in the design, including at least one meta block instance. The plurality of instances of functional blocks are displayed as respective graphical objects and identifiers of two or more implementations for the meta block instance from a meta block library are displayed. In response to designer selection of one implementation from the meta block library, a specification of the selected one implementation for the meta block instance is stored in association with the design. In response to designer selection of a graphical object corresponding to the at least one meta block instance, a designer-editable version of the one implementation is displayed. An updated specification of the one implementation associated with design is stored in response to designer modification of the designer-editable version of the one implementation.

Abstract translation: 组装电子电路设计的方法。 处理器执行包括在设计中实例化和耦合功能块的多个实例的操作，包括至少一个元块实例。 功能块的多个实例被显示为相应的图形对象，并且显示来自元块库的元块实例的两个或多个实现的标识符。 响应于来自元块库的一个实现的设计者选择，与设计相关联地存储元块实例的所选择的一个实现的规范。 响应于对应于至少一个元块实例的图形对象的设计者选择，显示该一个实现的设计者可编辑版本。 与设计相关联的一个实现的更新规范被存储以响应设计者修改该设计者可编辑版本的一个实现。

公开(公告)号：US07984091B1

公开(公告)日：2011-07-19

申请号：US11250741

申请日：2005-10-14

Applicant: Gabor Szedo

Inventor： Gabor Szedo

IPC: G06F1/02

CPC classification number: G06F1/035 ,  G06F17/142 ,  G06F17/17

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract translation: 描述了用于正弦曲线的二次逼近的插值器。 使用提供子采样组相位因子样本的一阶导数的样本源。 耦合微分器以接收第一阶导数并且被配置为提供一阶导数的二阶导数。 第一缩放装置被耦合以接收每个第一阶导数。 耦合第二微分器以接收第一阶导数中的每一个并且被配置为分别提供一阶导数的二阶导数。 第二缩放装置被耦合以接收二阶导数。 第一积分器被耦合以接收来自第一缩放装置的输出用于预加载，并且接收来自第二缩放装置的输出用于集成。 第三缩放装置被耦合以接收来自第一积分器的输出。 第二积分器被耦合以接收来自第三缩放装置的输出。

公开(公告)号：US08005881B1

公开(公告)日：2011-08-23

申请号：US11713261

申请日：2007-03-02

Applicant: Peter Szántó ,  Gabor Szedo ,  Béla Fehér ,  Wilson C. Chung

Inventor： Peter Szántó ,  Gabor Szedo ,  Béla Fehér ,  Wilson C. Chung

IPC: G06F17/10 ,  G06K9/40

CPC classification number: H03H17/0263 ,  G06T5/002 ,  G06T5/20 ,  G06T2200/28 ,  G06T2207/20192

Abstract: A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.

Abstract translation: 描述了可编程逻辑中的等级阶滤波器及其实例。 针对输入采样频率，滤波器窗口高度和输入样本数确定最大滤波器核心频率。 最大滤波芯频率大于采样频率。 最大滤波器核心频率可能不足以用于可编程逻辑中的秩序滤波器的字串行实例化。 秩序滤波器的完全并行实例化的大小在可编程逻辑中可能过大。 因此，对于具有超频的等级滤波器，实例化了部分平行的滤波器核。

公开(公告)号：US08713082B1

公开(公告)日：2014-04-29

申请号：US13180767

申请日：2011-07-12

Applicant: Peter Szanto ,  Gabor Szedo ,  Bela Feher ,  Wilson C. Chung

Inventor： Peter Szanto ,  Gabor Szedo ,  Bela Feher ,  Wilson C. Chung

IPC: G06F17/10

CPC classification number: H03H17/0263 ,  G06T5/002 ,  G06T5/20 ,  G06T2200/28 ,  G06T2207/20192

Abstract: A rank order filter and instantiation thereof in programmable logic is described. A maximum filter core frequency is determined for an input sampling frequency, a filter window height, and a number of input samples. The maximum filter core frequency is greater than the sampling frequency. The maximum filter core frequency may be insufficient for a word serial instantiation of the rank order filter in the programmable logic. The size of a fully parallel instantiation of the rank order filter may be excessive in programmable logic. Thus, a partially parallel filter core is instantiated for the rank order filter with overclocking.

Abstract translation: 描述了可编程逻辑中的等级阶滤波器及其实例。 针对输入采样频率，滤波器窗口高度和输入样本数确定最大滤波器核心频率。 最大滤波芯频率大于采样频率。 最大滤波器核心频率可能不足以用于可编程逻辑中的秩序滤波器的字串行实例化。 秩序滤波器的完全并行实例化的大小在可编程逻辑中可能过大。 因此，对于具有超频的等级滤波器，实例化了部分平行的滤波器核。

公开(公告)号：US08572148B1

公开(公告)日：2013-10-29

申请号：US12391231

申请日：2009-02-23

Applicant: Gabor Szedo ,  Hemang Parekh

Inventor： Gabor Szedo ,  Hemang Parekh

IPC: G06F15/00

CPC classification number: G06F17/142

Abstract: A data reorganizer for Fourier Transforms, both forward and inverse, of multiple parallel data streams input to an integrated circuit, and method for use thereof, are described. The data reorganizer has a k input commutator, for k a positive integer greater than zero; an address generator; memory buffers; and an output commutator.

Abstract translation: 描述了用于输入到集成电路的多个并行数据流的傅里叶变换的数据重组器（正向和反向）及其使用方法。 数据重组器具有k个输入换向器，k为大于零的正整数; 地址生成器 内存缓冲区 和一个输出换向器。

公开(公告)号：US07395293B1

公开(公告)日：2008-07-01

申请号：US10898628

申请日：2004-07-23

Applicant: Gabor Szedo ,  Helen Hai-Jo Tarn

Inventor： Gabor Szedo ,  Helen Hai-Jo Tarn

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: Various approaches for performing a fast-Fourier transform (FFT) of N input data elements using a radix K decomposition of the FFT are disclosed (K>=2, and N>=8). In one approach, N/K input data elements are written to respective ones of K addressable memories, and N/K*logK N passes are performed on the input data. Each pass includes reading K data elements in parallel from the K addressable memories using the respectively generated addresses, the K data elements being in a first order corresponding to the respective memories; permuting the first order of K data elements into a second order of K data elements; performing a radix K calculation on the second order of K data elements, resulting in corresponding result data elements in the second order; permuting the second order of K result data elements into the first order; and writing the K result data elements in parallel to the corresponding K addressable memories using the respective addresses.

Abstract translation: 公开了使用FFT的小数K分解来执行N个输入数据元素的快速傅里叶变换（FFT）的各种方法（K> = 2，并且N> = 8）。 在一种方法中，将N / K个输入数据元素写入K个可寻址存储器中的相应的一个，并且对输入数据执行N / K * log N N遍。 每次通过包括使用分别产生的地址从K个可寻址存储器中并行读取K个数据元素，K个数据元素处于与各个存储器对应的第一级; 将K个数据元素的第一顺序置换成K个数据元素的二阶; 对K个数据元素的二阶执行基数K计算，得到二阶对应的结果数据元素; 将K个结果数据元素的第二个顺序置换成第一个顺序; 并使用各自的地址将K个结果数据元素与相应的K个可寻址存储器并行地写入。

公开(公告)号：US08484267B1

公开(公告)日：2013-07-09

申请号：US12622327

申请日：2009-11-19

Applicant: Gabor Szedo

Inventor： Gabor Szedo

IPC: G06F7/00 ,  G06F7/44

CPC classification number: G06F7/5443 ,  G06F7/49936 ,  G06F7/535

Abstract: Weight normalization in hardware or software without a division operator is described, using only right bit shift, addition and subtraction operations. A right bit shift is performed on an expected sum to effectively divide the expected sum by two to provide a first updated value for the expected sum. An iteration is performed which includes: incrementing with a first adder a first variable by the first updated value of the expected sum to provide an updated value for the first variable; subtracting with a first subtractor a second weight from a first weight to provide a first updated value for the first weight; and performing a left bit shift on the second weight to effectively multiply the second weight by two to provide a first updated value for the second weight.

Abstract translation: 描述了没有除法运算符的硬件或软件的权重归一化，仅使用正确的位移，加法和减法运算。 对预期总和执行右位移位，以有效地将预期和除以2来提供预期总和的第一更新值。 执行迭代，其包括：用第一加法器递增预期和的第一更新值的第一变量，以提供第一变量的更新值; 用第一减法器从第一权重减去第二权重以提供第一权重的第一更新值; 以及对所述第二权重执行左位移，以有效地将所述第二权重乘以2，以提供所述第二权重的第一更新值。