公开(公告)号：US06689702B2

公开(公告)日：2004-02-10

申请号：US10304434

申请日：2002-11-25

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L21469

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

摘要翻译： 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

公开(公告)号：US06998357B2

公开(公告)日：2006-02-14

申请号：US10646034

申请日：2003-08-22

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L21/469

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

公开(公告)号：US06528856B1

公开(公告)日：2003-03-04

申请号：US09212773

申请日：1998-12-15

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L2976

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

摘要翻译： 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

公开(公告)号：US5858843A

公开(公告)日：1999-01-12

申请号：US722606

申请日：1996-09-27

申请人： Brian S. Doyle ,  David B. Fraser

发明人： Brian S. Doyle ,  David B. Fraser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/78391 ,  H01L29/66545

摘要： A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.

摘要翻译： 公开了一种形成用于制造半导体集成电路的场效应晶体管结构的方法。 该方法利用了新的加工顺序，其中在形成栅极电介质和栅电极之前进行高温处理步骤。 处理顺序如下进行：将待形成的栅极的复制图案化的掩模沉积在衬底上。 然后，进行形成掺杂区域的高温步骤。 然后，进行形成硅化物的高温步骤。 接下来，将平坦化材料沉积在掩模上并被平坦化。 选择性地将掩模移除到平坦化材料以在平坦化材料内形成开口。 栅极电介质和栅电极形成在开口内。

公开(公告)号：US5818092A

公开(公告)日：1998-10-06

申请号：US794231

申请日：1997-01-30

申请人： Gang Bai ,  David B. Fraser

发明人： Gang Bai ,  David B. Fraser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L29/4941 ,  H01L29/665

摘要： A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

摘要翻译： 一种形成多硅化物薄膜的方法。 首先，形成硅层。 接下来，在第一硅层上形成薄的阻挡层。 然后在阻挡层上形成第二硅层。 接下来，在第二硅层上形成金属层。 然后金属层和第二硅层一起反应形成硅化物。

公开(公告)号：US5714418A

公开(公告)日：1998-02-03

申请号：US555491

申请日：1995-11-08

申请人： Gang Bai ,  David B. Fraser

发明人： Gang Bai ,  David B. Fraser

IPC分类号： H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76864 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76834

摘要： An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.

公开(公告)号：US5977634A

公开(公告)日：1999-11-02

申请号：US954221

申请日：1997-10-20

申请人： Gang Bai ,  David B. Fraser

发明人： Gang Bai ,  David B. Fraser

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76864 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76834

摘要： An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.

摘要翻译： 包括扩散阻挡层的电互连结构和在半导体衬底上形成结构的方法。 在衬底上形成双层扩散阻挡层。 屏障包括阻挡层下面的捕获层。 阻挡层比捕获层厚，并且与捕获层不反应。 然后在阻挡层上形成比阻挡层厚的导电层。 当导电层与阻挡层的阻挡层不反应时，导电层与屏障的捕获层是反应的。

公开(公告)号：US5861340A

公开(公告)日：1999-01-19

申请号：US602126

申请日：1996-02-15

申请人： Gang Bai ,  David B. Fraser

发明人： Gang Bai ,  David B. Fraser

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L29/4941 ,  H01L29/665

摘要： A method of forming a polycide thin film. First, a silicon layer is formed. Next, a thin barrier layer is formed on the first silicon layer. A second silicon layer is then formed on the barrier layer. Next, a metal layer is formed on the second silicon layer. The metal layer and the second silicon layer are then reacted together to form a silicide.

摘要翻译： 一种形成多硅化物薄膜的方法。 首先，形成硅层。 接下来，在第一硅层上形成薄的阻挡层。 然后在阻挡层上形成第二硅层。 接下来，在第二硅层上形成金属层。 然后金属层和第二硅层一起反应形成硅化物。

公开(公告)号：US5536684A

公开(公告)日：1996-07-16

申请号：US269440

申请日：1994-06-30

申请人： M. Lawrence A. Dass ,  Peng Cheng ,  David B. Fraser

发明人： M. Lawrence A. Dass ,  Peng Cheng ,  David B. Fraser

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/2257 ,  Y10S148/015 ,  Y10S148/035 ,  Y10S148/147

摘要： A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer. If the cobalt silicide layer after the ion implantation contain dopants, then during the anneal the dopants are driven out of the cobalt silicide layer and diffuse into the silicon substrate to form a conformal shallow junction. The resulting structure can be used in the vertical integration of microelectronic devices. In other words, the resulting structure is suitable for growing selective epitaxial silicon, for growing epitaxial insulators, for processing devices above the silicide in that epitaxial silicon, and for processing devices with buried conductors.

摘要翻译： 用于形成平面外延钴硅化物并形成用于半导体处理的浅共形结的方法。 形成硅化钴和氮化钛双层。 化学去除氮化钛层。 然后将具有或不具有掺杂剂的离子注入到硅化钴层中。 在离子注入期间，将至少一部分硅化钴层转变为无定形钴硅混合物，而非非晶部分保持单晶。 如果离子注入包含掺杂剂，则在注入完成之后，硅化钴层的非晶态部分和非非晶部分均含有掺杂剂。 然后将衬底在包含氮气的环境中或在氧化环境中退火。 在退火期间，硅衬底的非晶部分再结晶成单晶硅化钴层。 如果离子注入后的硅化钴层含有掺杂剂，则在退火期间，掺杂剂被驱出钴硅化物层并扩散到硅衬底中以形成共形的浅结。 所得结构可用于微电子器件的垂直集成。 换句话说，所得结构适于生长选择性外延硅，用于生长外延绝缘体，用于在该外延硅中的硅化物上方处理器件，以及用于处理具有埋入导体的器件。

公开(公告)号：US06303464B1

公开(公告)日：2001-10-16

申请号：US08774382

申请日：1996-12-30

申请人： Eng T. Gaw ,  Quat T. Vu ,  David B. Fraser ,  Chien Chiang ,  Ian A. Young ,  Thomas N. D. Marieb

发明人： Eng T. Gaw ,  Quat T. Vu ,  David B. Fraser ,  Chien Chiang ,  Ian A. Young ,  Thomas N. D. Marieb

IPC分类号： H01L2176

CPC分类号： H01L21/7682

摘要： A reduced capacitance interconnect system. A first metal layer is formed to a predetermined level above a first dielectric layer which is formed on a semiconductor substrate. The first metal layer level forms multiple interconnect lines wherein each interconnect line is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal layer and in the trenches between the interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.

摘要翻译： 降低电容互连系统。 第一金属层形成在形成在半导体衬底上的第一介电层上方的预定水平。 第一金属层级形成多个互连线，其中每个互连线通过包括具有最高纵横比的沟槽的沟槽与每个相邻的互连线分开。 在第一金属层和互连线之间的沟槽中形成第二电介质层，使得具有空隙尖端的封闭空隙与金属层的顶部基本一致地形成在至少每个沟槽中，其纵横比高于 预定的最小纵横比，其中具有最高纵横比的沟槽中的封闭空隙具有至少占沟槽体积的15％的空隙体积。