公开(公告)号：US06689702B2

公开(公告)日：2004-02-10

申请号：US10304434

申请日：2002-11-25

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L21469

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

摘要翻译： 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

公开(公告)号：US06998357B2

公开(公告)日：2006-02-14

申请号：US10646034

申请日：2003-08-22

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L21/469

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

公开(公告)号：US06528856B1

公开(公告)日：2003-03-04

申请号：US09212773

申请日：1998-12-15

申请人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David B. Fraser ,  Brian S. Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L2976

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

摘要翻译： 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

公开(公告)号：US20050087820A1

公开(公告)日：2005-04-28

申请号：US10646034

申请日：2003-08-22

申请人： Gang Bai ,  David Fraser ,  Brian Doyle ,  Peng Cheng ,  Chunlin Liang

发明人： Gang Bai ,  David Fraser ,  Brian Doyle ,  Peng Cheng ,  Chunlin Liang

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28229 ,  H01L29/517

摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

摘要翻译： 形成适合用作金属氧化物半导体场效应晶体管（MOSFET）的栅极电介质层的电介质层的方法包括氧化硅衬底的表面，在氧化表面上形成金属层，并使金属 与氧化表面形成超过衬底的基本上本征的硅层，其中硅层的至少一部分可以是外延硅层，以及位于硅层之上的金属氧化物层。 在本发明的另一方面，集成电路包括多个MOSFET，其中多个晶体管中的各个晶体管具有金属氧化物栅极电介质层和位于金属氧化物电介质层之下的基本上本征的硅层。

公开(公告)号：US06204103B1

公开(公告)日：2001-03-20

申请号：US09157114

申请日：1998-09-18

申请人： Gang Bai ,  Brian S. Doyle

发明人： Gang Bai ,  Brian S. Doyle

IPC分类号： H01L218238

CPC分类号： H01L21/823842

摘要： The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.

摘要翻译： 本发明提供一种形成第一和第二晶体管器件的方法。 硅化物的第一区域形成在覆盖半导体衬底中的第一阱区的栅极电介质的第一部分上。 硅化物的第二区域形成在栅极电介质的第二部分上。 栅极电介质的第二部分覆盖半导体衬底中的第二阱区。 第一和第二掺杂结区域分别形成在第一和第二阱区中。

公开(公告)号：US07187044B2

公开(公告)日：2007-03-06

申请号：US09517705

申请日：2000-03-02

申请人： Chunlin Liang ,  Gang Bai

发明人： Chunlin Liang ,  Gang Bai

IPC分类号： H01L29/76

CPC分类号： H01L21/823842

摘要： A method for making circuit device that includes a first transistor having a first metal gate electrode overlying a first gate dielectric on a first area of a semiconductor substrate. The first gate electrode has a work function corresponding to the work function of one of P-type silicon and N-type silicon. The circuit device also includes a second transistor coupled to the first transistor. The second transistor has a second metal gate electrode over a second gate dielectric on a second area of the semiconductor substrate. The second gate metal gate electrode has a work function corresponding to the work function of the other one of P-type silicon and N-type silicon.

摘要翻译： 一种制造电路器件的方法，包括：第一晶体管，其具有覆盖在半导体衬底的第一区域上的第一栅极电介质的第一金属栅电极。 第一栅电极具有对应于P型硅和N型硅之一的功函数的功函数。 电路装置还包括耦合到第一晶体管的第二晶体管。 第二晶体管在半导体衬底的第二区域上的第二栅极电介质上具有第二金属栅电极。 第二栅极金属栅电极具有对应于另一个P型硅和N型硅的功函数的功函数。

公开(公告)号：US06794232B2

公开(公告)日：2004-09-21

申请号：US10383842

申请日：2003-03-07

申请人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

发明人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

IPC分类号： H01I21337

CPC分类号： H01L21/82345 ,  H01L21/823425 ,  H01L27/088

摘要： Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

摘要翻译： 具有至少两层材料的栅电极的绝缘栅场效应晶体管提供类似于掺杂多晶硅的栅电极功函数值，消除多余耗效应并且还基本上防止杂质扩散入栅电介质。 公开了用于n沟道FET的相对厚的Al和薄TiN的双层堆叠以及相对厚的Pd和薄TiN的双层堆叠，或者用于p沟道FET的相对厚的Pd和薄TaN。 改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。

公开(公告)号：US06373111B1

公开(公告)日：2002-04-16

申请号：US09451696

申请日：1999-11-30

申请人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

发明人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

IPC分类号： H01L2976

CPC分类号： H01L21/82345 ,  H01L21/823425 ,  H01L27/088

摘要： Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

摘要翻译： 具有至少两层材料的栅电极的绝缘栅场效应晶体管提供类似于掺杂多晶硅的栅电极功函数值，消除多余耗效应，并且还基本上防止杂质向栅电介质的扩散。 公开了用于n沟道FET的相对厚的Al和薄TiN的双层堆叠以及相对厚的Pd和薄TiN的双层堆叠，或者用于p沟道FET的相对厚的Pd和薄TaN。 改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。

公开(公告)号：US6166417A

公开(公告)日：2000-12-26

申请号：US109993

申请日：1998-06-30

申请人： Gang Bai ,  Chunlin Liang

发明人： Gang Bai ,  Chunlin Liang

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/823842

摘要： A transistor device includes a gate dielectric overlying a substrate, a barrier layer overlying the gate dielectric, and a gate electrode overlying the barrier layer. The barrier layer of the device has a physical property that inhibits interaction between the gate dielectric and the gate electrode.

公开(公告)号：US06790731B2

公开(公告)日：2004-09-14

申请号：US10071144

申请日：2002-02-06

申请人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

发明人： Jun-Fei Zheng ,  Brian Doyle ,  Gang Bai ,  Chunlin Liang

IPC分类号： H01L21336

CPC分类号： H01L21/82345 ,  H01L21/823425 ,  H01L27/088

摘要： A method for creating insulated gate field effect transistors having gate electrodes with at least two layers of materials to provide gate electrode work function values that are similar to those of doped polysilicon, to eliminate the poly depletion effect, and to substantially prevent impurity diffusion into the gate dielectric. Depositing bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs is disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

摘要翻译： 一种用于制造具有至少两层材料的栅电极的绝缘栅场效应晶体管的方法，以提供类似于掺杂多晶硅的栅电极功函数值，以消除多余耗尽效应，并且基本上防止杂质扩散到 栅电介质。 公开了用于p沟道FET的n沟道FET和相对厚的Pd和薄TiN或相对厚的Pd和薄TaN的双层堆叠的相对厚的Al和薄TiN的双层堆叠。 改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。