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1.发明申请Dynamic Data Transfer Control Method and Apparatus for Shared SMP Computer Systems 有权用于共享SMP计算机系统的动态数据传输控制方法和装置公开(公告)号：US20090070498A1
公开(公告)日：2009-03-12
申请号：US11853881
申请日：2007-09-12
申请人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
发明人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
IPC分类号： G06F3/00
CPC分类号： G06F13/4059 , G06F12/0859
摘要： As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.
摘要翻译： 由于对计算机系统数据总线的性能关键（高速或全速）请求沿中央管线行进，系统检测接口数据总线当前是否为空或正在进行半速传输。 如果存在持续的低速传输，则系统动态地将交织缓冲器中的读取速率移动或减慢到一半速度，并且利用空闲的一半带宽。 由于数据总线不可用，这种动态的“拉链”或数据的时间偏移可防止管道传递被拒绝。
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2.发明授权Dynamic data transfer control method and apparatus for shared SMP computer systems 有权用于共享SMP计算机系统的动态数据传输控制方法和装置公开(公告)号：US07574548B2
公开(公告)日：2009-08-11
申请号：US11853881
申请日：2007-09-12
申请人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
发明人： Garrett M. Drapala , Deanna P. Dunn , Michael Fee
CPC分类号： G06F13/4059 , G06F12/0859
摘要： As a performance critical (high or full speed) request for a computer system data bus travels down a central pipeline, the system detects whether the interface data bus is currently empty or there is an ongoing half-speed transfer. If there is an ongoing low speed transfer, the system dynamically time shift or slows down the read rate out of the interleave buffer to half speed, and utilizes the free half of the bandwidth. This dynamic “zippering” or time shifting of data prevents a pipe pass from being rejected because the whole data bus is unavailable.
摘要翻译： 由于对计算机系统数据总线的性能关键（高速或全速）请求沿中央管线行进，系统检测接口数据总线当前是否为空或正在进行半速传输。 如果存在持续的低速传输，则系统动态地将交织缓冲器中的读取速率移动或减慢到一半速度，并且利用空闲的一半带宽。 由于数据总线不可用，这种动态的“拉链”或数据的时间偏移可防止管道传递被拒绝。
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公开(公告)号：US07779189B2
公开(公告)日：2010-08-17
申请号：US12035249
申请日：2008-02-21
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译： 一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线 第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到 所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。 相应的系统和计算机程序产品。
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4.发明申请公开(公告)号：US20090216933A1
公开(公告)日：2009-08-27
申请号：US12035249
申请日：2008-02-21
IPC分类号： G06F13/36
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译： 一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线 第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到 所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。 相应的系统和计算机程序产品。
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公开(公告)号：US20130339608A1
公开(公告)日：2013-12-19
申请号：US13495373
申请日：2012-06-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
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公开(公告)号：US08478920B2
公开(公告)日：2013-07-02
申请号：US12822333
申请日：2010-06-24
IPC分类号： G06F13/00
CPC分类号： G06F13/26
摘要： A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.
摘要翻译： 提供了一种用于控制共享总线上的数据流中断的机制。 接收到第一个要求来传输数据。 为第一个请求确定高优先级数据组件和低优先级数据组件。 高优先级数据组件无间断地传输。 响应于在传送高优先级数据组件时的接收请求，接收到的请求被拒绝。
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公开(公告)号：US20110320778A1
公开(公告)日：2011-12-29
申请号：US12821933
申请日：2010-06-23
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译： 在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。 多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。 该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。
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8.发明申请公开(公告)号：US20110320722A1
公开(公告)日：2011-12-29
申请号：US12821744
申请日：2010-06-23
CPC分类号： G06F12/084 , G06F12/0855
摘要： An apparatus for controlling access to a pipeline includes a plurality of command queues including a first subset of the plurality of command queues being assigned processes the commands of first command type, a second subset of the plurality of command queues being assigned to process commands of the second command type, and a third subset of the plurality of the command queues not being assigned to either the first subset or the second subset. The apparatus also includes an input controller configured to receive requests having the first command type and the second command type and assign requests having the first command type to command queues in the first subset until all command queues in the first subset are filled and then assign requests having the first command type to command queues in the third subset.
摘要翻译： 一种用于控制对流水线的访问的装置，包括多个命令队列，包括被分配处理第一命令类型的命令的多个命令队列的第一子集，多个命令队列的第二子集被分配给 第二命令类型，并且多个命令队列的第三子集未被分配给第一子集或第二子集。 该装置还包括输入控制器，其被配置为接收具有第一命令类型和第二命令类型的请求，并且分配具有第一命令类型的请求来命令第一子集中的队列，直到第一子集中的所有命令队列被填满，然后分配请求 具有第一种命令类型来命令第三个子集中的队列。
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9.发明申请Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer 失效在多节点对称多处理计算机中管理并发序列化中断广播命令公开(公告)号：US20110320665A1
公开(公告)日：2011-12-29
申请号：US12821752
申请日：2010-06-23
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
摘要翻译： 在多节点对称多处理计算机中管理并发的串行化中断广播命令，包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签，每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单，该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令，则由通信适配器 将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。
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10.发明申请Method for Expediting Return of Line Exclusivity to a Given Processor in a Symmetric Multiprocessing Data Processing System 失效在对称多处理数据处理系统中加速返回给定处理器的排除独占性的方法公开(公告)号：US20090193194A1
公开(公告)日：2009-07-30
申请号：US12021403
申请日：2008-01-29
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.
摘要翻译： 一种用于在多节点数据处理系统中消除通过改进的系统总线管理，处理器交叉无效堆栈以及可导致这些所请求的高速缓存操作的系统操作的高速缓冲存储器中线路排他性的争用的方法和装置 拒绝。
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