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公开(公告)号：US20130339608A1
公开(公告)日：2013-12-19
申请号：US13495373
申请日：2012-06-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
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2.发明授权公开(公告)号：US08918587B2
公开(公告)日：2014-12-23
申请号：US13495373
申请日：2012-06-13
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0884 , G06F12/123
摘要： Embodiments relate to accessing a cache line on a multi-level cache system having a system memory. Based on a request for exclusive ownership of a specific cache line at the local node, requests are concurrently sent to the system memory and remote nodes of the plurality of nodes for the specific cache line by the local node. The specific cache line is found in a specific remote node. The specific remote node is one of the remote nodes. The specific cache line is removed from the specific remote node for exclusive ownership by another node. Based on the specified node having the specified cache line in ghost state, any subsequent fetch request is initiated for the specific cache line from the specific node encounters the ghost state. When the ghost state is encountered, the subsequent fetch request is directed only to nodes of the plurality of nodes.
摘要翻译： 实施例涉及在具有系统存储器的多级缓存系统上访问高速缓存行。 基于本地节点对特定高速缓存线的独占所有权的请求，请求被本地节点同时发送到用于特定高速缓存行的多个节点的系统内存和远程节点。 在特定的远程节点中找到特定的高速缓存行。 特定的远程节点是远程节点之一。 从特定的远程节点中删除特定的高速缓存行以供另一个节点独占所有。 基于具有指定缓存行在幽灵状态的指定节点，任何后续的提取请求将针对具体的缓存行启动，特定的缓存行遇到幽灵状态。 当遇到鬼状态时，后续的提取请求仅被引导到多个节点的节点。
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3.发明授权Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效在多节点对称多处理计算机中维护高速缓存一致性公开(公告)号：US08762651B2
公开(公告)日：2014-06-24
申请号：US12821578
申请日：2010-06-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本 的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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4.发明授权Maintaining cache coherence in a multi-node, symmetric multiprocessing computer 失效在多节点对称多处理计算机中维护高速缓存一致性公开(公告)号：US08423736B2
公开(公告)日：2013-04-16
申请号：US12816464
申请日：2010-06-16
IPC分类号： G06F12/00
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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5.发明申请Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效维持多节点对称多处理计算机中的缓存一致性公开(公告)号：US20110320738A1
公开(公告)日：2011-12-29
申请号：US12821578
申请日：2010-06-23
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/084
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first compute node to other compute nodes a request for the cache line; if at least two of the compute nodes has a correct copy of the cache line, selecting which compute node is to transmit the correct copy of the cache line to the first node, and transmitting from the selected compute node to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由所述第一计算节点向高速缓存未命中的高速缓存发送对所述高速缓存行的请求; 如果至少两个计算节点具有高速缓存行的正确副本，则选择哪个计算节点将高速缓存行的正确副本发送到第一节点，以及从所选择的计算节点向第一节点发送正确的副本 的缓存行; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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6.发明申请Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer 失效维持多节点对称多处理计算机中的缓存一致性公开(公告)号：US20110314228A1
公开(公告)日：2011-12-22
申请号：US12816464
申请日：2010-06-16
CPC分类号： G06F12/0833
摘要： Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
摘要翻译： 在多节点对称多处理计算机中维护高速缓存一致性，所述计算机由多个计算节点组成，所述计算机节点包括：由第一计算节点对高速缓存未命中的高速缓存行的请求进行广播; 从每个其他计算节点向所有其他节点传送该节点上的高速缓存行的状态，包括从具有正确副本的任何计算节点向第一节点发送正确的高速缓存行副本; 并且根据所有节点中的高速缓存行的一个或多个状态，由每个节点更新每个节点中的高速缓存行的状态。
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公开(公告)号：US20120210070A1
公开(公告)日：2012-08-16
申请号：US13450871
申请日：2012-04-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0895
摘要： A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory.
摘要翻译： 提供了一种数据缓冲机制。 高速缓存的一部分被分配为缓冲区，高速缓存的另一部分被指定为随机存取存储器（RAM）。 一个缓冲区被分配给一个处理器。 根据处理器的指令将数据块存储到高速缓冲存储器的一个缓冲区。 数据块从缓存的缓冲区中的一个存储到存储器。
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公开(公告)号：US20110320730A1
公开(公告)日：2011-12-29
申请号：US12821963
申请日：2010-06-23
CPC分类号： G06F12/0895
摘要： A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory.
摘要翻译： 提供了一种数据缓冲机制。 高速缓存的一部分被分配为缓冲区，高速缓存的另一部分被指定为随机存取存储器（RAM）。 一个缓冲区被分配给一个处理器。 根据处理器的指令将数据块存储到高速缓冲存储器的一个缓冲区。 数据块从缓存的缓冲区中的一个存储到存储器。
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9.发明申请Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer 失效在多节点对称多处理计算机中管理并发序列化中断广播命令公开(公告)号：US20110320665A1
公开(公告)日：2011-12-29
申请号：US12821752
申请日：2010-06-23
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
摘要翻译： 在多节点对称多处理计算机中管理并发的串行化中断广播命令，包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签，每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单，该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令，则由通信适配器 将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。
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10.发明授权公开(公告)号：US07779189B2
公开(公告)日：2010-08-17
申请号：US12035249
申请日：2008-02-21
CPC分类号： G06F13/36
摘要： A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product.
摘要翻译： 一种用于流水线仲裁的方法，包括从第一流水线接收对共享芯片接口的第一请求，确定第一请求是否需要共享芯片接口的响应总线，以及如果确定不需要响应总线 第一请求，认为第一请求仅需要共享芯片接口的地址总线，对从第二管道接收的用于访问地址总线的共享芯片接口的第二请求仲裁第一请求，将第一请求发送到 所述地址总线如果所述第一请求通过所述第二请求获胜所述仲裁，并且如果所述第二请求通过所述第一请求获胜仲裁，则拒绝所述第一请求。 相应的系统和计算机程序产品。
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