公开(公告)号：US4000487A

公开(公告)日：1976-12-28

申请号：US562362

申请日：1975-03-26

申请人： Garvin Wesley Patterson ,  William A. Shelly ,  Earnest M. Monahan

发明人： Garvin Wesley Patterson ,  William A. Shelly ,  Earnest M. Monahan

IPC分类号： G06F9/46 ,  G06F13/00 ,  G06F13/14 ,  G06F13/22 ,  G06F13/26 ,  G06F13/40 ,  G06F3/00

CPC分类号： G06F13/22 ,  G06F13/26 ,  G06F13/4022

摘要： An input/output processing system includes a plurality of active modules, a plurality of passive modules, at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. The active modules include an input/output processing unit which processes interrupts and executes command sequences and a multiplexer unit which directly controls transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. The system interface unit which operatively provides connections between the different modules includes apparatus for generating steering codes defining the physical location of each module requiring service by another module of the system. The system interface unit appends information provided by the particular module generating a requesting request for attention to the steering code generated. The generation of steering code information by the system interface unit and the module included in such requests insures that only authorized accesses are made to the different modules during the input/output processing unit's execution of programs during the running of processes associated therewith.

摘要翻译： 输入/输出处理系统包括多个有源模块，多个无源模块，至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。 有源模块包括处理中断并执行命令序列的输入/输出处理单元和直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。 可操作地提供不同模块之间的连接的系统接口单元包括用于产生定义需要系统的另一个模块进行服务的每个模块的物理位置的转向代码的装置。 系统接口单元附加由特定模块提供的信息，产生请求请求，以产生注意力。 由系统接口单元和包括在该请求中的模块产生导向码信息确保在输入/输出处理单元在与其相关的进程运行期间执行程序期间仅对不同模块进行授权访问。

公开(公告)号：US4006466A

公开(公告)日：1977-02-01

申请号：US562364

申请日：1975-03-26

申请人： Garvin Wesley Patterson ,  William A. Shelly ,  Jaime Calle ,  Earnest M. Monahan

发明人： Garvin Wesley Patterson ,  William A. Shelly ,  Jaime Calle ,  Earnest M. Monahan

IPC分类号： G06F13/12 ,  G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F1/00

CPC分类号： G06F9/4812 ,  G06F13/26 ,  G06F9/4818 ,  G06F9/4831

摘要： An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.

摘要翻译： 输入/输出数据处理系统包括多个有源模块，多个无源模块和至少一个存储器模块和具有多个端口的系统接口单元，每个端口连接到不同的模块之一。 每个模块通过多个不同的接口连接到一个端口。 有源模块包括用于处理中断和执行命令序列的输入/输出处理单元和用于直接控制存储器模块与耦合到多路复用器单元的多个端口中的不同端口的任何外围设备之间的传输的多路复用器单元。 系统的不同模块包括用于将命令信息传送到多路复用器单元的可编程接口和与其相关联的设备，以使不同类型的控制与输入/输出数据传送操作并行进行。 每个多路复用器单元包括多个存储寄存器，其可操作地耦合到与其相关联的可编程接口，用于接收控制信息，从而指定由该单元给予的优先级，以处理从与其相关联的设备接收的不同类型的中断信号， 指定用于维护中断的一组处理例程中的哪一个的信息。

公开(公告)号：US4099234A

公开(公告)日：1978-07-04

申请号：US741632

申请日：1976-11-15

申请人： John M. Woods ,  Marion G. Porter ,  Donald V. Mills ,  Edward F. Weller, III ,  Garvin Wesley Patterson ,  Earnest M. Monahan

发明人： John M. Woods ,  Marion G. Porter ,  Donald V. Mills ,  Edward F. Weller, III ,  Garvin Wesley Patterson ,  Earnest M. Monahan

IPC分类号： G06F11/18 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F13/00 ,  G06F15/16 ,  G06F11/00

CPC分类号： G06F11/1641 ,  G06F11/0745 ,  G06F11/079 ,  G06F11/165 ,  G06F11/2089 ,  G06F11/22

摘要： An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwithstanding the fact that the first processing unit tests well. Following reconfiguration, the operating system associated with the system provides periodic testing of the good processing unit, thereby ensuring that the system continues to operate reliably.

摘要翻译： 输入/输出系统至少包括一对处理单元和系统接口装置，用于在主处理单元或主处理单元的控制下在正常系统操作期间比较两对的两半所产生的结果。 系统接口装置包括比较电路，用于检测每一半的结果与序列控制逻辑电路之间的错误比较，序列控制逻辑电路在发生误比较时进行解锁或解除配置，以预定的方式建立 处理单元有故障。 系统接口设备在处理单元内具有一定的最小置信度的信号指示，继续使用存储的诊断例程对处理器进行测试，以确定处理单元中的哪一个是良好的。 然后停止坏处理单元的操作，并使良好处理单元能够继续系统运行。 为了确保可靠的处理，尽管第一个处理单元测试良好，但是当误差比较不能与与该对中的一个相关联的错误状况不相关时，该对的两个部分被测试。 在重新配置之后，与系统相关联的操作系统提供良好处理单元的周期性测试，从而确保系统继续可靠地运行。

公开(公告)号：US4091455A

公开(公告)日：1978-05-23

申请号：US752345

申请日：1976-12-20

申请人： John M. Woods ,  Marion G. Porter ,  Earnest M. Monahan

发明人： John M. Woods ,  Marion G. Porter ,  Earnest M. Monahan

IPC分类号： G06F13/12 ,  G06F11/07 ,  G06F11/22 ,  G06F11/273 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  G06F11/00

CPC分类号： G06F11/0772 ,  G06F11/0745 ,  G06F11/2294

摘要： An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the logical pair preventing the disconnected processing unit from communicating with other modules. The control logic circuits further include circuits which in response to special commands from a good processor are operative to condition via a special line, circuits in the disconnected processing unit to apply status signals representative of the contents of a control register to the system interface unit. The other circuits within the system interface unit in response to a further command condition certain switching circuit networks for loading the status signals into one of the registers included in the system interface unit for subsequent analysis by system routines.

摘要翻译： 输入/输出处理系统包括多个模块，其包括连接以作为逻辑对操作的至少一对处理单元和具有多个端口的系统接口单元。 每个端口连接到不同的模块之一，用于互连模块对，用于通过包括在系统接口单元中的多个交换电路网络进行通信。 系统接口单元还包括用于断开逻辑对的每个处理器的控制逻辑电路，防止断开的处理单元与其他模块通信。 控制逻辑电路还包括电路，其响应于来自良好处理器的特殊命令可操作以经由特殊线路进行调节，断开处理单元中的电路将代表控制寄存器的内容的状态信号应用于系统接口单元。 系统接口单元内的其他电路响应于另外的命令条件，某些转换电路网络将状态信号加载到系统接口单元中包括的寄存器之一中，以便随后由系统程序进行分析。

公开(公告)号：US4070704A

公开(公告)日：1978-01-24

申请号：US686975

申请日：1976-05-17

申请人： Jaime Calle ,  Robert J. Garvey ,  Earnest M. Monahan ,  George L. Parris ,  Jerome J. Twibell ,  John M. Woods

发明人： Jaime Calle ,  Robert J. Garvey ,  Earnest M. Monahan ,  George L. Parris ,  Jerome J. Twibell ,  John M. Woods

IPC分类号： G06F11/20 ,  G06F15/177 ,  G06F11/00 ,  G06F13/00

CPC分类号： G06F15/177 ,  G06F11/20

摘要： An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

摘要翻译： 自动重新配置硬件功能，用于在输入/输出处理器引导加载的启动阶段发生故障时自动更改本地内存/处理器配置并重新启动引导加载顺序。 当引导加载请求源自系统控制台或中央系统时，自动重新配置逻辑被启用。 一旦引导启动请求，就可以尝试所有可能的本地存储器/输入输出处理器（IOPP）配置，而无需进一步的手动干预。 如果没有配置成功，I0P配置面板上将显示引导加载错误指示。

公开(公告)号：US4028664A

公开(公告)日：1977-06-07

申请号：US562314

申请日：1975-03-26

申请人： Earnest M. Monahan ,  Garvin W. Patterson

发明人： Earnest M. Monahan ,  Garvin W. Patterson

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/26 ,  G06F15/16 ,  G06F15/177 ,  G06F9/18

CPC分类号： G06F9/4812 ,  G06F13/26 ,  G06F9/462 ,  G06F9/4818

摘要： A dispatcher mechanism for assigning to a processor the highest priority peripheral having the highest priority request. In a data processing system having at least one processor, and a plurality of peripheral devices coupled to a system interface unit SIU utilized for communication between said processor and peripheral devices, and also having a plurality of processes competing for control of said processor, a priority interrupt mechanism determines the highest priority peripheral having the highest priority request and then provides an interrupt signal to the processor. A release instruction REL is used to exit the process. The dispatcher mechanism dispatches data to the processor upon request from the processor in order to give control of the processor to the highest priority request.

摘要翻译： 一种用于向处理器分配具有最高优先级请求的最高优先级的外设的调度机构。 在具有至少一个处理器和多个外围设备的数据处理系统中，耦合到用于所述处理器和外围设备之间的通信的系统接口单元SIU，并且还具有多个处理器来竞争所述处理器的控制，优先级 中断机制确定具有最高优先级请求的最高优先级外设，然后向处理器提供中断信号。 释放指令REL用于退出该过程。 调度机构根据处理器的请求将数据分配给处理器，以便将处理器的控制权授予最高优先权请求。

公开(公告)号：US4001783A

公开(公告)日：1977-01-04

申请号：US562315

申请日：1975-03-26

申请人： Earnest M. Monahan ,  Garvin W. Patterson ,  Jaime Calle

发明人： Earnest M. Monahan ,  Garvin W. Patterson ,  Jaime Calle

IPC分类号： G06F9/46 ,  G06F13/26 ,  G06F9/18 ,  G06F15/16

CPC分类号： G06F13/26

摘要： Priority interrupt hardware monitors for the existence of, and determines the relative importance of requests to determine or attempt to determine when to interrupt an executing process on a processor. The processor may be interrupted only when the hardware determines that something more important needs to be done than what is being done by the currently executing process. Additionally, the processor may set interrupts for itself so that a portion of an executing process may be executed at a higher priority than that required for the remaining portion of the same process.