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    Method and apparatus for calculating a page table index from a virtual address
    1.
    发明授权
    Method and apparatus for calculating a page table index from a virtual address 有权

    公开(公告)号：US06393544B1

    公开(公告)日：2002-05-21

    申请号：US09430793

    申请日：1999-10-31

    申请人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  James O. Hays ,  Jerome C. Huck ,  Jonathan K. Ross ,  Sunil Saxena ,  Koichi Yamada

    发明人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  James O. Hays ,  Jerome C. Huck ,  Jonathan K. Ross ,  Sunil Saxena ,  Koichi Yamada

    IPC分类号： G06F1200

    CPC分类号： G06F12/1018 ,  G06F2212/652

    摘要： A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2K bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2L bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

    Method and apparatus for pre-validating regions in a virtual addressing scheme
    3.
    发明授权
    Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
    用于在虚拟寻址方案中预先验证区域的方法和装置

    公开(公告)号：US06408373B2

    公开(公告)日：2002-06-18

    申请号：US09850878

    申请日：2001-05-07

    申请人： Stephen G. Burger ,  James O. Hays ,  Jonathan K. Ross ,  William R. Bryg ,  Rajiv Gupta ,  Gary N. Hammond ,  Koichi Yamada

    发明人： Stephen G. Burger ,  James O. Hays ,  Jonathan K. Ross ,  William R. Bryg ,  Rajiv Gupta ,  Gary N. Hammond ,  Koichi Yamada

    IPC分类号： G06F1200

    CPC分类号： G06F12/1036

    摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.

    摘要翻译： 一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。 通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。 根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID） 字段，保护和访问属性字段以及物理页号（PPN）字段。 此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。 当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。 另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。 当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。 搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。 如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。 如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

    Apparatus and method for a load bias--load with intent to semaphore
    7.
    发明授权
    Apparatus and method for a load bias--load with intent to semaphore 失效
    用于信号量的负载偏置负载的装置和方法

    公开(公告)号：US6128706A

    公开(公告)日：2000-10-03

    申请号：US018165

    申请日：1998-02-03

    申请人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

    发明人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

    IPC分类号： G06F9/312 ,  G06F13/00

    CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30087

    摘要： Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardware cache to try to maintain ownership until the next memory reference from that processor. When used with the Cmpxchg instruction semaphore operation, the Load-Bias instruction will reduce coherency traffic, and minimize the possibility of coherency ping-ponging or system deadlock that causes the condition in which no processor is getting useful work done.

    摘要翻译： 用于有效地共享数据以支持硬件高速缓存一致性并利用信号量指令在软件中协调的装置和方法。 因此，称为“负载偏置”的新指令除了正常的加载操作之外，还请求数据的私有副本，并向硬件缓存提示，以尝试维持所有权，直到来自该处理器的下一个存储器引用。 当与Cmpxchg指令信号量操作一起使用时，负载偏移指令将减少一致性流量，并最大限度地减少一致性乒乓或系统死锁的可能性，从而导致无处理器无法正常工作的条件。

    Method and apparatus for transferring data in a computer system
    8.
    发明授权
    Method and apparatus for transferring data in a computer system 失效
    用于在计算机系统中传送数据的方法和装置

    公开(公告)号：US06199144B1

    公开(公告)日：2001-03-06

    申请号：US09001336

    申请日：1997-12-31

    申请人： Judge K. Arora ,  William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

    发明人： Judge K. Arora ,  William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  Michael L. Ziegler

    IPC分类号： G06F1200

    CPC分类号： G06F12/0833

    摘要： A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.

    摘要翻译： 一种用于将数据从计算机系统中的第一存储器位置传送到第二存储器位置的方法和装置。 执行加载指令，并且作为响应，在单个总线事务期间，数据从第一存储器位置传送到第二存储器位置。 在相同的总线事务期间，如果加载指令指示这样做，则请求使存储在第三存储器位置的数据的副本无效。

    Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address
    9.
    发明授权
    Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address 失效
    使用至少一种默认页面大小和为虚拟地址空间选择的页面大小之一的页表步行器将滑动字段放置在虚拟地址中

    公开(公告)号：US06088780A

    公开(公告)日：2000-07-11

    申请号：US829337

    申请日：1997-03-31

    申请人： Koichi Yamada ,  Gary N. Hammond ,  Jim Hays ,  Jonathan Kent Ross ,  Stephen Burger ,  William R. Bryg

    发明人： Koichi Yamada ,  Gary N. Hammond ,  Jim Hays ,  Jonathan Kent Ross ,  Stephen Burger ,  William R. Bryg

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1009 ,  G06F2212/652

    摘要： A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.

    摘要翻译： 一种用于实现使用为虚拟地址空间选择的默认页面大小和页面大小中的至少一个来定位虚拟地址中的滑动字段的页表行进者的方法和装置。 根据本发明的一个方面，提供了一种在计算机系统中使用的装置，其包括页面大小存储区域和页表行进器。 页面大小存储区域用于存储每个被选择用于翻译不同虚拟地址集合的页面大小的数量。 页表步行器包括耦合到页面大小存储区域的选择单元以及耦合到选择单元的页面输入地址生成器。 对于接收到的每个虚拟地址，选择单元基于为了翻译该虚拟地址所属的虚拟地址集而选择的页面大小来定位该虚拟地址中的字段。 响应于接收到为每个虚拟地址标识的字段中的比特，页面入口地址生成器基于这些比特识别页表中的条目。

    Method and apparatus for instruction and data serialization in a computer processor
    10.
    发明授权
    Method and apparatus for instruction and data serialization in a computer processor 失效
    计算机处理器中指令和数据串行化的方法和装置

    公开(公告)号：US6006325A

    公开(公告)日：1999-12-21

    申请号：US769784

    申请日：1996-12-19

    申请人： Stephen Burger ,  Gary N. Hammond ,  William R. Bryg

    发明人： Stephen Burger ,  Gary N. Hammond ,  William R. Bryg

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/30087 ,  G06F9/3834

    摘要： A new instruction that ensures that the effects of a control register write will be observed at a well defined time is introduced. Specifically, the present invention introduces the concept of a serialization fence instruction. The serialization fence instruction ensures that after a control register in a computer has been modified, all subsequent instructions will observe the effects of the control register modification. Two different serialization fence instructions are illustrated: a data memory reference serialization fence instruction (SRLZ.d) and an instruction fetch serialization fence instruction (SRLZ.i). The data memory reference serialization fence instruction ensures that subsequent instruction executions and data memory references will observe the effects of the control register write. The instruction fetch serialization fence instruction ensures that the entire machine pipeline, starting at the initial instruction fetch stage, will observe the effects of the control register write.

    摘要翻译： 介绍了一个新的指令，确保控制寄存器写入的效果将在明确的时间内被观察到。 具体地，本发明引入了序列化栅栏指令的概念。 序列化栅栏指令确保在计算机中的控制寄存器已被修改后，所有后续指令将观察到控制寄存器修改的影响。 说明了两个不同的序列化栅栏指令：数据存储器引用序列化栅栏指令（SRLZ.d）和指令获取序列化栅栏指令（SRLZ.i）。 数据存储器引用序列化栅栏指令确保后续指令执行和数据存储器引用将观察到控制寄存器写入的影响。 指令获取序列化栅栏指令确保从初始指令读取阶段开始的整个机器流水线将观察到控制寄存器写入的影响。