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    Method and apparatus for pre-validating regions in a virtual addressing scheme
    1.
    发明授权
    Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
    用于在虚拟寻址方案中预先验证区域的方法和装置

    公开(公告)号：US06408373B2

    公开(公告)日：2002-06-18

    申请号：US09850878

    申请日：2001-05-07

    申请人： Stephen G. Burger ,  James O. Hays ,  Jonathan K. Ross ,  William R. Bryg ,  Rajiv Gupta ,  Gary N. Hammond ,  Koichi Yamada

    发明人： Stephen G. Burger ,  James O. Hays ,  Jonathan K. Ross ,  William R. Bryg ,  Rajiv Gupta ,  Gary N. Hammond ,  Koichi Yamada

    IPC分类号： G06F1200

    CPC分类号： G06F12/1036

    摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.

    摘要翻译： 一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。 通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。 根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID） 字段，保护和访问属性字段以及物理页号（PPN）字段。 此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。 当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。 另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。 当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。 搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。 如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。 如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

    Method and apparatus for calculating a page table index from a virtual address
    2.
    发明授权
    Method and apparatus for calculating a page table index from a virtual address 有权

    公开(公告)号：US06393544B1

    公开(公告)日：2002-05-21

    申请号：US09430793

    申请日：1999-10-31

    申请人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  James O. Hays ,  Jerome C. Huck ,  Jonathan K. Ross ,  Sunil Saxena ,  Koichi Yamada

    发明人： William R. Bryg ,  Stephen G. Burger ,  Gary N. Hammond ,  James O. Hays ,  Jerome C. Huck ,  Jonathan K. Ross ,  Sunil Saxena ,  Koichi Yamada

    IPC分类号： G06F1200

    CPC分类号： G06F12/1018 ,  G06F2212/652

    摘要： A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, and does not store tags or chain links. A single “long format” page table is provided for the entire system, supports chained segments, and includes hash tag fields. The method of the present invention forms an entry address from a virtual address, with the entry address referencing an entry of the page table. To form the entry address, first a hash page number is formed from the virtual address by shifting the virtual address right based on the page size of the region of the virtual address. If the computer system is operating with long format page tables, the next step is to form a hash index by combining the hash page number and the region identifier referenced by the region portion of the virtual address, and to form a table offset by shifting the hash index left by K bits, wherein each long format page table entry is 2K bytes long. However, if the computer system is operating with short format page tables, the next step is to form a hash index by setting the hash index equal to the hash page number, and to form a table offset by shifting the hash index left by L bits, wherein each short format page table entry is 2L bytes long. Next, a mask is formed based on the size of the page table. A first address portion is then formed using the base address of the page table and the mask, and a second address portion is formed using the table offset and the mask. Finally, the entry address is formed by combining the first and second address portions. By providing a single algorithm capable of generating a page table entry for both long and short format page tables, the present invention reduces the amount of logic required to access both page table formats, without significantly affecting execution speed.

    Method and apparatus for pre-validating regions in a virtual addressing scheme
    6.
    发明授权
    Method and apparatus for pre-validating regions in a virtual addressing scheme 失效
    用于在虚拟寻址方案中预先验证区域的方法和装置

    公开(公告)号：US06230248B1

    公开(公告)日：2001-05-08

    申请号：US09170140

    申请日：1998-10-12

    申请人： Stephen G. Burger ,  James O. Hays ,  Jonathan K. Ross ,  William R. Bryg ,  Rajiv Gupta ,  Gary N. Hammon ,  Koichi Yamada

    发明人： Stephen G. Burger ,  James O. Hays ,  Jonathan K. Ross ,  William R. Bryg ,  Rajiv Gupta ,  Gary N. Hammon ,  Koichi Yamada

    IPC分类号： G06F1216

    CPC分类号： G06F12/1036

    摘要： A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time. When a virtual-to-physical entry is established for a page in a region having an RID stored in a region register, the RID and VRN are stored in the appropriate fields of the TLB entry. In addition, the valid field is set and the rpV field is set to indicate that the TLB entry contains an active VRN-to-RID mapping, thereby pre-validating the region. When a physical address is translated into a virtual address, a VRN and a VPN are extracted from the virtual address and provided to the TLB. The TLB is searched to find an entry having a set valid field, a set rpV field, and VRN and VPN fields containing entries matching the VRN and VPN extracted from the virtual address. If such an entry is found, the protection and access attributes field is used to determine whether the requested access is allowed. If the requested access is allowed, the PPN from the PPN field of the TLB entry is combined with an offset from the virtual address to produce a physical address that is used to complete the memory access.

    摘要翻译： 一种方法和装置通过将虚拟区域号（VRN）位和区域标识符（RID）存储在翻译后备缓冲器（TLB）条目中来对虚拟寻址方案中的区域进行预验证。 通过将VRN位和RID都存储在TLB表中，可以在执行大多数TLB访问时旁路区域寄存器，从而去除区域寄存器中TLB查找过程的关键路径并提高系统性能。 根据本发明的TLB包括具有有效字段，区域预验证有效（rpV）字段，虚拟区域号（VRN）字段，虚拟页号（VPN）字段），区域标识符（RID） 字段，保护和访问属性字段以及物理页号（PPN）字段。 此外，一组区域寄存器包含在任何给定时间处于活动状态的RID。 当在具有存储在区域寄存器中的RID的区域中的页面建立虚拟到物理条目时，RID和VRN被存储在TLB条目的相应字段中。 另外，设置有效字段，并且设置rpV字段以指示TLB条目包含活动的VRN到RID映射，从而预先验证该区域。 当物理地址被转换为虚拟地址时，从虚拟地址提取VRN和VPN，并提供给TLB。 搜索TLB以找到具有设置的有效字段，集合rpV字段的条目，以及包含与从虚拟地址提取的VRN和VPN匹配的条目的VRN和VPN字段。 如果找到这样的条目，则使用保护和访问属性字段来确定所请求的访问是否被允许。 如果允许所请求的访问，则来自TLB条目的PPN字段的PPN与来自虚拟地址的偏移组合，以产生用于完成存储器访问的物理地址。

    Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
    9.
    发明授权
    Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效
    具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统

    公开(公告)号：US07281116B2

    公开(公告)日：2007-10-09

    申请号：US10903200

    申请日：2004-07-30

    申请人： Jonathan K. Ross ,  Dale Morris

    发明人： Jonathan K. Ross ,  Dale Morris

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027 ,  G06F2212/682

    摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.

    摘要翻译： 本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。 与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。 因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。

    Method and apparatus for managing access to out-of-frame registers
    10.
    发明授权
    Method and apparatus for managing access to out-of-frame registers 有权
    用于管理对帧外寄存器的访问的方法和装置

    公开(公告)号：US07272702B2

    公开(公告)日：2007-09-18

    申请号：US10702252

    申请日：2003-11-06

    申请人： Achmed Rumi Zahir ,  Cary A. Coutant ,  Carol L. Thompson ,  Jonathan K. Ross

    发明人： Achmed Rumi Zahir ,  Cary A. Coutant ,  Carol L. Thompson ,  Jonathan K. Ross

    IPC分类号： G06F9/34

    CPC分类号： G06F9/30123 ,  G06F9/30134 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3861

    摘要： Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack including a plurality of register stack frames. Each of the register stack frames includes zero or more registers. One of the plurality of register stack frames is a current register stack frame. When execution of the instruction requires writing to a register referenced by the instruction, the instruction execution unit determines whether the register referenced by the instruction is within the current register stack frame. If the instruction execution unit determines that the register is not within the current register stack frame, the instruction execution unit does not execute the instruction and may, for example, generate a fault. The instruction execution unit executes the instruction is the instruction execution unit determines that the register is within the current register stack frame. When execution of the instruction requires reading from a register referenced by the instruction, the instruction execution unit executes the instruction whether or not the register referenced by the instruction is within the current register stack frame.

    摘要翻译： 公开了用于管理对当前寄存器堆栈帧之外的寄存器的访问的方法和装置。 处理器中的指令执行单元接收要执行的指令。 处理器包括寄存器堆栈，寄存器堆栈包括多个寄存器堆栈帧。 每个寄存器堆栈帧包括零个或多个寄存器。 多个寄存器堆栈帧中的一个是当前寄存器堆栈帧。 当执行指令需要写入由指令引用的寄存器时，指令执行单元确定该指令引用的寄存器是否在当前寄存器堆栈帧内。 如果指令执行单元确定寄存器不在当前寄存器堆栈帧内，则指令执行单元不执行指令，并且例如可能产生故障。 指令执行单元执行指令是指令执行单元确定寄存器在当前寄存器堆栈帧内。 当指令的执行需要从指令引用的寄存器读取时，指令执行单元执行指令，该指令是否由指令引用的寄存器是否在当前寄存器堆栈帧内。