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公开(公告)号：US06324672B1
公开(公告)日：2001-11-27
申请号：US09505600
申请日：2000-02-16
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.
摘要翻译： 提供了一种指定设计参数的方法，用于配置可编程IC的电路。 描述电路的设计数据库在计算机屏幕显示器上以基于表格的格式显示。 设计数据库可以包括存储图，包括要放置在目标可编程IC中的位存储空间中的数据。 该设计数据库不需要电路的原理图或HDL描述，即使对于复杂的应用特定电路也是如此。 所需的参数由用户输入，通常使用切换按钮，下拉菜单或键盘输入。 然后将选定的参数输入设计数据库，从而根据所选参数配置设计数据库。 接下来，将设计数据库通过诸如因特网的数据通信链路传送到编译软件所在的第二计算机。 然后编译设计，并将所得到的网表传回原始计算机。 在一个实施例中，示意符号或HDL实例化也由第二计算机产生，并被发送回始发计算机。
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公开(公告)号：US6023565A
公开(公告)日：2000-02-08
申请号：US805378
申请日：1997-02-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.
摘要翻译： 提供了一种指定设计参数的方法，用于配置可编程IC的电路。 描述电路的设计数据库在计算机屏幕显示器上以基于表格的格式显示。 设计数据库可以包括存储图，包括要放置在目标可编程IC中的位存储空间中的数据。 该设计数据库不需要电路的原理图或HDL描述，即使对于复杂的应用特定电路也是如此。 所需的参数由用户输入，通常使用切换按钮，下拉菜单或键盘输入。 然后将选定的参数输入设计数据库，从而根据所选参数配置设计数据库。 接下来，将设计数据库通过诸如因特网的数据通信链路传送到编译软件所在的第二计算机。 然后编译设计，并将所得到的网表传回原始计算机。 在一个实施例中，示意符号或HDL实例化也由第二计算机产生，并被发送回始发计算机。
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公开(公告)号：US6118938A
公开(公告)日：2000-09-12
申请号：US832989
申请日：1997-04-04
CPC分类号： G06F17/5054
摘要： A table-based computer user interface and a method of providing design parameters are provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for application-specific circuits and other complicated circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters and memory map data are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. In one embodiment, the user interface can also be used to display read data from a previously programmed programmable IC.
摘要翻译： 提供了一种基于桌面的计算机用户界面和提供设计参数的方法，用于配置可编程IC的电路。 描述电路的设计数据库在计算机屏幕显示器上以基于表格的格式显示。 设计数据库可以包括存储图，包括要放置在目标可编程IC中的位存储空间中的数据。 该设计数据库不需要电路的原理图或HDL描述，即使是专用电路和其他复杂电路。 所需的参数由用户输入，通常使用切换按钮，下拉菜单或键盘输入。 然后将所选择的参数和存储器映射数据输入到设计数据库中，从而根据所选参数配置设计数据库。 在一个实施例中，用户界面也可用于显示来自先前编程的可编程IC的读取数据。
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公开(公告)号：US06381732B1
公开(公告)日：2002-04-30
申请号：US09924357
申请日：2001-08-07
IPC分类号： H03K19177
CPC分类号： G06F21/76
摘要： A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.
摘要翻译： 提供了可选择性地接受或拒绝所选软件（宏）的现场可编程门阵列（FPGA）。 具体来说，FPGA的配置数据通过配置端口传递给解码器。 解码器处理配置数据以检测锁定的宏。 如果检测到锁定的宏，则解码器尝试使用存储在FGPA的密钥表中的一个或多个密钥解锁锁定的宏。 如果密钥表中有一个相应的密钥，解码器解锁锁定的宏以配置FPGA。 密钥可以由宏供应商预编程到FGPA中。 如果包含锁定宏的配置数据在没有适当键的情况下与FPGA一起使用，则FPGA的配置将失败。
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公开(公告)号：US06357037B1
公开(公告)日：2002-03-12
申请号：US09232022
申请日：1999-01-14
IPC分类号： G06F1750
CPC分类号： G06F21/76 , G06F17/5054
摘要： A method is provided for configuring an FPGA to accept or reject selected software (macros). Specifically, if an end user desires to use a locked macro from a first macro vendor a locked macro from a second macro vendor in the same FPGA, a key manager prepares a keyed FPGA for the end user by pre-programming an FPGA with a first key, which is configured to unlock the first locked macro, and a second key, which is configured to unlock the second locked macro. The key manager obtains the first key from the first macro vendor and the second key from the second macro vendor. The keys are stored in a key table of the FPGA that is write-only from outside the FPGA. The end user pays a fee to the key manager for the keyed macro, but is not given access to the keys. The key manager apportions the fee from the end user and distributes appropriate licensing fees to the first macro vendor and the second macro vendor.
摘要翻译： 提供了一种用于配置FPGA以接受或拒绝所选软件（宏）的方法。 具体来说，如果终端用户希望使用来自第一宏供应商的锁定宏来自同一FPGA中的第二宏供应商的锁定宏，则密钥管理器通过对第一个FPGA的预编程来为最终用户准备一个带键的FPGA 键，其被配置为解锁第一锁定宏，以及第二键，其被配置为解锁第二锁定宏。 密钥管理器从第一个宏供应商获取第一个密钥，从第二个宏供应商获取第二个密钥。 密钥存储在FPGA的关键表中，FPGA的外部是只写的。 最终用户向键控宏的密钥管理者支付费用，但是不能访问密钥。 主要经理从最终用户分配费用，并向第一个宏供应商和第二个宏供应商分配适当的许可费用。
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公开(公告)号：US06324676B1
公开(公告)日：2001-11-27
申请号：US09232021
申请日：1999-01-14
IPC分类号： G06F1750
CPC分类号： G06F21/76
摘要： A field programmable gate array (FPGA) is provided that can selectively accept or reject selected software (macros). Specifically, configuration data for the FPGA is passed through a configuration port to a decoder. The decoder processes the configuration data to detect locked macros. If a locked macro is detected, the decoder attempts to unlock the locked macro using one or more keys stored in a key table of the FGPA. If an appropriate key is in the key table, the decoder unlocks the locked macro to configure the FPGA. The keys can be pre-programmed into the FGPA by the macro vendor. If configuration data containing a locked macro is used with an FPGA without the appropriate key, configuration of the FPGA fails.
摘要翻译： 提供了可选择性地接受或拒绝所选软件（宏）的现场可编程门阵列（FPGA）。 具体来说，FPGA的配置数据通过配置端口传递给解码器。 解码器处理配置数据以检测锁定的宏。 如果检测到锁定的宏，则解码器尝试使用存储在FGPA的密钥表中的一个或多个密钥解锁锁定的宏。 如果密钥表中有一个相应的密钥，解码器解锁锁定的宏以配置FPGA。 密钥可以由宏供应商预编程到FGPA中。 如果包含锁定宏的配置数据在没有适当键的情况下与FPGA一起使用，则FPGA的配置将失败。
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7.发明授权System and method for controlled performance degradation in electronic circuits 失效电子电路中受控性能下降的系统和方法
公开(公告)号：US6078209A
公开(公告)日：2000-06-20
申请号：US114379
申请日：1998-07-13
申请人： Joseph D. Linoff
发明人： Joseph D. Linoff
IPC分类号： H03K19/003 , H03K21/00 , H03K17/14
CPC分类号： H03K19/00369
摘要： A system and method for altering the effective operating frequency of an electronic system (e.g., an IC) in response to changes in temperature or current provides controlled and deliberate performance degradation. Reducing the effective operating frequency at high temperatures allows an IC to maintain a relatively stable power consumption. A first embodiment of the invention includes a temperature transducer, an Analog-to-Digital (A/D) converter, a select generator, and a clock frequency divider. The temperature transducer measures the temperature, which is converted by the A/D converter to a digital value. The digital temperature value drives the select generator, which generates one or more select signals. The select signals control the clock frequency divider to produce a clock signal with an effective clock frequency that depends on the measured temperature. According to a second embodiment of the invention, a current transducer is used instead of a temperature transducer.
摘要翻译： 响应于温度或电流的变化而改变电子系统（例如，IC）的有效工作频率的系统和方法提供受控且有意的性能下降。 降低高温下的有效工作频率允许IC保持相对稳定的功耗。 本发明的第一实施例包括温度传感器，模数（A / D）转换器，选择发生器和时钟分频器。 温度传感器测量由A / D转换器转换为数字值的温度。 数字温度值驱动选择发生器，其产生一个或多个选择信号。 选择信号控制时钟分频器以产生具有取决于测量温度的有效时钟频率的时钟信号。 根据本发明的第二实施例，使用电流传感器代替温度传感器。
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8.发明授权Circuit and method for generating clock signals with an incrementally reduced effective frequency 失效用于产生具有逐渐减小的有效频率的时钟信号的电路和方法
公开(公告)号：US6043692A
公开(公告)日：2000-03-28
申请号：US114380
申请日：1998-07-13
申请人： Joseph D. Linoff
发明人： Joseph D. Linoff
CPC分类号： H03K23/66
摘要： The present invention provides a novel clock frequency divider that accepts an input clock having an input clock frequency and provides an output clock with an effective clock frequency of one of 1/N, 2/N, . . . , (N-1)/N, N/N times the input clock frequency, where N is an integer. The clock frequency divider of the present invention divides the input clock frequency asymmetrically by filtering out one or more of each N pulses on the input clock, as dictated by select signals. For example, in a clock frequency divider having N=8, a first clock output signal filters out one of each eight pulses, retaining seven pulses. Therefore, the effective frequency of the output clock signal is (N-1)/N, or 7/8, times the frequency of input clock signal. Similarly, a second output clock signal retains six of every eight pulses, a third retains five, and so forth.
摘要翻译： 本发明提供了一种新颖的时钟分频器，其接收具有输入时钟频率的输入时钟，并提供具有1 / N，2 / N之一的有效时钟频率的输出时钟。 。 。 ，（N-1）/ N，N / N倍于输入时钟频率，其中N是整数。 本发明的时钟分频器按照选择信号的指示，通过对输入时钟上的每个N个脉冲中的一个或多个进行滤波，来对输入时钟频率进行非对称分频。 例如，在具有N = 8的时钟分频器中，第一时钟输出信号滤除每八个脉冲中的一个，保持七个脉冲。 因此，输出时钟信号的有效频率为（N-1）/ N或+ E，fra 7/8 + EE，乘以输入时钟信号的频率。 类似地，第二输出时钟信号保留每八个脉冲中的六个脉冲，三分之一保持五个等等。
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9.发明授权
公开(公告)号：US5594363A
公开(公告)日：1997-01-14
申请号：US418972
申请日：1995-04-07
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.
摘要翻译： 本发明提供了一种FPGA集成电路，其具有由非易失性存储单元形成的可编程开关互连的逻辑单元和互连线阵列。 逻辑单元被设计为根据单元内的可编程开关的设置来提供逻辑或存储器功能。 阵列中的逻辑单元可通过本地，长和全局布线段的层次结构互连。 互连通过布线段之间的可编程开关的设置来实现。
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