System, apparatus, and method for limiting non-volatile memory
    1.
    发明授权
    System, apparatus, and method for limiting non-volatile memory 有权
    用于限制非易失性存储器的系统,装置和方法

    公开(公告)号:US07051223B2

    公开(公告)日:2006-05-23

    申请号:US10677152

    申请日:2003-09-30

    IPC分类号: G06F12/16

    CPC分类号: G06F11/1441

    摘要: An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module configured to determine an amount of volatile computer memory allocated for use in a computer and a memory adjustment module configured to adjust the amount of volatile computer memory allocated for use in the computer based on the amount of available energy in the auxiliary power source. A startup module may be configured to allow the computer to begin moving data normally when the memory adjustment module limits volatile computer memory allocated for use by the computer to a minimum level and the energy monitor module determines that the amount of available energy in the auxiliary power source has reached a minimum level capable of transferring the volatile computer memory allocated for use by the computer to non-volatile computer memory during a computer shutdown.

    摘要翻译: 基于辅助电源中的可用能量来限制易失性计算机存储器的装置包括被配置为确定辅助电源中的可用能量的能量监测模块。 还提供了一种存储器状态模块,其被配置为确定分配用于计算机的易失性计算机存储器的量和存储器调整模块,所述存储器调整模块被配置为基于可用能量的量来调整分配用于计算机中的易失性计算机存储器的数量 辅助电源。 启动模块可以被配置为当存储器调整模块将分配供计算机使用的易失性计算机存储器限制在最小水平时允许计算机开始正常地移动数据,并且能量监视器模块确定辅助功率中的可用能量的量 源已经达到能够在计算机关闭期间将分配给计算机使用的易失性计算机存储器传送到非易失性计算机存储器的最小级别。

    Data length control of access to a data bus
    3.
    发明授权
    Data length control of access to a data bus 失效
    访问数据总线的数据长度控制

    公开(公告)号:US06636913B1

    公开(公告)日:2003-10-21

    申请号:US09551861

    申请日:2000-04-18

    IPC分类号: G06F1300

    CPC分类号: G06F13/126

    摘要: A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.

    摘要翻译: 一种用于控制访问总线以用于以多字节数据流的形式传送数据的方法和系统。 数据传输代理被耦合到请求访问总线以在其上传送数据。 用于控制对总线的访问的系统包括响应于数据传输代理的访问请求的总线仲裁器,一次授予对一个数据传输代理的总线访问。 在授权访问期间,数据长度计数器累积指示在总线和数据传送代理之间传送的数据的长度的信号。 数据长度计数器指示传输预定长度的数据的完成,并且总线仲裁器逻辑响应指示传送完成的数据长度计数器,导致总线仲裁器终止对数据传输代理的访问许可。 因此,对总线访问的控制基于精确测量传输数据的长度,而不是基于定时器。

    Tracking and control of prefetch data in a PCI bus system
    4.
    发明授权
    Tracking and control of prefetch data in a PCI bus system 失效
    跟踪和控制PCI总线系统中的预取数据

    公开(公告)号:US06578102B1

    公开(公告)日:2003-06-10

    申请号:US09551862

    申请日:2000-04-18

    IPC分类号: G06F1300

    CPC分类号: G06F13/4059

    摘要: A system and method track and control the prefetching of blocks of a data stream in a PCI bus system, avoiding unnecessary prefetches. The data stream is grouped into major blocks which comprise a fixed plurality of contiguous blocks. A prefetch buffer stores the blocks of data prefetched from a PCI data source for transfer to a requester. First and second associated prefetch count storage locations store first and second counts initialized by prefetch initialization logic. The first count represents the number of blocks of data of a major block of the data, and the second count represents the total number of the blocks of the data stream to be prefetched, less the initialized number of blocks of the first count. As each block of data is prefetched, a prefetch counter decrements the first count by a number representing the block of data. As the prefetch counter decrements the first count to zero, prefetch count logic stops the prefetch, allowing completion of the transfer of the prefetched data to the data destination. Thus, the second count represents the next remaining number of blocks to be prefetched, and the requester can rotate to a different read request at the end of a major block, knowing the next major block will not be prefetched until requested.

    摘要翻译: 系统和方法跟踪和控制PCI总线系统中数据流块的预取,避免不必要的预取。 数据流被分组成包括固定的多个相邻块的主要块。 预取缓冲器将从PCI数据源预取的数据块存储到请求者。 第一和第二相关联的预取计数存储位置存储通过预取初始化逻辑初始化的第一和第二计数。 第一计数表示数据的主要块的数据块的数量,第二计数表示要预取的数据流的块的总数,少于初始数的块的初始化数。 当每个数据块被预取时,预取计数器将第一个计数器递减一个表示数据块的数字。 当预取计数器将第一计数器递减到零时,预取计数逻辑停止预取,从而允许完成将预取数据传送到数据目的地。 因此,第二计数表示要预取的块的下一个剩余数量,并且请求者可以在主块的结尾处旋转到不同的读请求,知道下一个主块将不被预取,直到被请求为止。

    Flushing stale data from a PCI bus system read prefetch buffer
    5.
    发明授权
    Flushing stale data from a PCI bus system read prefetch buffer 有权
    从PCI总线系统刷新过期数据读取预取缓冲区

    公开(公告)号:US06490647B1

    公开(公告)日:2002-12-03

    申请号:US09542917

    申请日:2000-04-04

    IPC分类号: G06F1336

    CPC分类号: G06F13/4059

    摘要: A system and method for flushing stale data from a read prefetch buffer of a PCI bus system which transfers data in the form of data streams of contiguous blocks. The PCI bus system comprises a channel adapter at one PCI bus that issues read commands, a data source coupled to a second PCI bus, and a prefetch buffer that prefetches the blocks of read data. A prefetch counter posts the remaining number blocks to be read and transferred, posting the prefetch count at a storage location of a storage memory mapped to a prefetch location in the prefetch buffer. The prefetch count is written to the storage location by a prefetch count write command. The system for flushing stale data from the prefetch buffer comprises a key detector for sensing an unique identifier of the prefetch count write command. Data path logic responds to the key detector, determining the prefetch location of the prefetch buffer from the mapped storage location of the prefetch count write command, and flushing any prefetch data at the determined prefetch location.

    摘要翻译: 用于从PCI总线系统的读取预取缓冲器中刷新过期数据的系统和方法,其以连续块的数据流的形式传送数据。 PCI总线系统包括在一个PCI总线处发出读命令的通道适配器,耦合到第二PCI总线的数据源,以及预读取数据块的预取缓冲器。 预取计数器发布要读取和传送的剩余数字块,在预取缓冲器中映射到预取位置的存储存储器的存储位置发布预取计数。 预取计数通过预取计数写入命令写入存储位置。 用于从预取缓冲器冲洗过期数据的系统包括用于感测预取计数写入命令的唯一标识符的密钥检测器。 数据路径逻辑响应密钥检测器,从预取计数写入命令的映射存储位置确定预取缓冲器的预取位置,以及在确定的预取位置处刷新任何预取数据。

    Validating stored copies of data images to load into memory
    7.
    发明授权
    Validating stored copies of data images to load into memory 失效
    验证存储的数据映像副本加载到内存中

    公开(公告)号:US08521707B2

    公开(公告)日:2013-08-27

    申请号:US13444378

    申请日:2012-04-11

    IPC分类号: G06F7/00 G06F17/00

    摘要: Provided are a method, system, and article of manufacture for validating stored copies of data images to load into memory. An image of data is maintained in a memory, wherein the image in the memory includes a generation number. The image in the memory is written to at least two copies of the image to storage locations in response to a first event, wherein the generation number for the image in the memory is stored in the storage locations having the copies of the image. A check generation number is stored in a storage location. The image is loaded from at least one of the copies of the image in one of the storage locations to the memory in response to a second event The generation number for the image loaded into the memory. The check generation number is incremented in response to the second event. The generation numbers for the copies of the image in the storage locations and the check generation number are used to validate the copies of the image.

    摘要翻译: 提供了用于验证存储的数据图像的副本以加载到存储器中的方法,系统和制品。 数据的图像被保存在存储器中,其中存储器中的图像包括代数。 响应于第一事件,存储器中的图像被写入到图像的至少两个副本到存储位置,其中存储器中的图像的生成号码存储在具有图像的副本的存储位置中。 检查代号存储在存储位置。 响应于第二事件,将图像从存储位置之一中的图像的副本中的至少一个加载到存储器。加载到存储器中的图像的生成号码。 检查生成号码响应于第二个事件而递增。 用于存储位置中的图像的副本的生成编号和检查生成号用于验证图像的副本。

    Memory preserved cache to prevent data loss
    9.
    发明授权
    Memory preserved cache to prevent data loss 失效
    内存保存缓存以防止数据丢失

    公开(公告)号:US07975169B2

    公开(公告)日:2011-07-05

    申请号:US12132087

    申请日:2008-06-03

    IPC分类号: G06F11/00

    摘要: A method, system, and computer program product for preserving data in a storage subsystem having dual cache and dual nonvolatile storage (NVS) through a failover from a failed cluster to a surviving cluster is provided. A memory preserved indicator is initiated to mark tracks on a cache of the surviving cluster to be preserved, the tracks having an image in an NVS of the failed cluster. A destage operation is performed to destage the marked tracks. Subsequent to a determination that each of the marked tracks have been destaged, the memory preserved indicator is disabled to remove the mark from the tracks. If the surviving cluster reboots previous to each of the marked tracks having been destaged, the cache is verified as a memory preserved cache, the marked tracks are retained for processing while all unmarked tracks are removed, and the marked tracks are processed.

    摘要翻译: 提供了一种用于通过从故障集群到存活集群的故障转移来保存具有双缓存和双非易失性存储(NVS)的存储子系统中的数据的方法,系统和计算机程序产品。 启动存储器保存的指示符以标记要保留的存活簇的高速缓存上的轨道,轨道在故障集群的NVS中具有图像。 执行了一个停船操作,以排除标记的轨迹。 在确定每个标记的轨道已经停止之后,禁用存储器保留指示符以从轨道中移除标记。 如果幸存的群集在已经去往每个标记的轨道之前重新启动,则将高速缓存验证为存储器保存的高速缓存,标记的轨道被保留用于处理,而所有未标记的轨道被移除,并且标记的轨道被处理。

    WEAR LEVELING OF SOLID STATE DISKS DISTRIBUTED IN A PLURALITY OF REDUNDANT ARRAY OF INDEPENDENT DISK RANKS
    10.
    发明申请
    WEAR LEVELING OF SOLID STATE DISKS DISTRIBUTED IN A PLURALITY OF REDUNDANT ARRAY OF INDEPENDENT DISK RANKS 有权
    在多个冗余的独立磁盘阵列阵列中分散固定状态磁盘的等级

    公开(公告)号:US20100332749A1

    公开(公告)日:2010-12-30

    申请号:US12495244

    申请日:2009-06-30

    IPC分类号: G06F12/16 G06F12/02

    摘要: A computational device allocates a plurality of solid state disks to a plurality of redundant array of independent disk (RAID) ranks, wherein a different solid state disk is absent in each RAID rank of the plurality of RAID ranks. The computational device determines at least one selected solid state disk from the plurality of solid state disks, wherein the at least one selected solid state disk is estimated to have undergone a greater amount of wear in comparison to other solid state disks in the plurality of solid state disks. Relatively more data and parity information is written to those RAID ranks in which the at least one selected solid state disk is absent in comparison to those RAID ranks in which the at least one selected solid state disk is present.

    摘要翻译: 计算设备将多个固态磁盘分配给独立磁盘(RAID)等级的多个冗余阵列,其中在多个RAID等级的每个RAID等级中不存在不同的固态磁盘。 计算装置从多个固态盘确定至少一个所选择的固态盘,其中与多个固体中的其他固态盘相比,所述至少一个所选择的固态盘被估计已经经历了更大量的磨损 状态磁盘。 与存在至少一个所选固态盘的那些RAID等级相比,将相对更多的数据和奇偶校验信息写入到其中不存在至少一个所选固态盘的那些RAID等级。