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    ANALOG MOS CIRCUITS HAVING REDUCED VOLTAGE STRESS
    1.
    发明申请
    ANALOG MOS CIRCUITS HAVING REDUCED VOLTAGE STRESS 失效
    具有降低电压应力的模拟MOS电路

    公开(公告)号：US20060145751A1

    公开(公告)日：2006-07-06

    申请号：US10905436

    申请日：2005-01-04

    申请人： Gautam Gangasani ,  Louis Hsu ,  Karl Selander ,  Steven Zier

    发明人： Gautam Gangasani ,  Louis Hsu ,  Karl Selander ,  Steven Zier

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262

    摘要： Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET. A switching network is operable to controllably switch the first and second FETs and the third switching element between a powered on state in which the first and second currents are conducted and the third switching element is conducting, and a powered off state in which the first and second currents are not conducted and the third switching element is nonconducting such that the same drain to source voltage stress is applied to both first and second FETs.

    摘要翻译： 提供电路和方法用于降低施加到FET的漏极/源极传导路径的电压应力和/或减小对可能具有薄栅极氧化物的FET的栅极氧化物的应力。 因此，在本文公开的电流镜电路中，第一场效应晶体管（FET）具有第一栅极和第一漏极，其中第一漏极导电连接到用于导电第一电流的电流源。 电流镜电路还包括具有导电连接到第一栅极的第二栅极的至少一个第二FET，其中第二FET可操作以输出与第一电流固定比例的第二电流。 具有第一导电端子的开关元件连接到第一栅极和第二栅极，第二导电端子连接到第一FET的第一漏极。 开关网络可操作以在第一和第二电流被导通的导通状态和第三开关元件导通之间可控地切换第一和第二FET和第三开关元件，以及断电状态，其中第一和第二开关 不传导第二电流，第三开关元件不导通，使得相同的漏极/源极电压应力施加到第一和第二FET。

    METHOD TO AVOID DEVICE STRESSING
    2.
    发明申请
    METHOD TO AVOID DEVICE STRESSING 有权
    避免设备压力的方法

    公开(公告)号：US20070096797A1

    公开(公告)日：2007-05-03

    申请号：US11163688

    申请日：2005-10-27

    申请人： Hibourahima Camara ,  Louis Hsu ,  James Rockrohr ,  Karl Selander ,  Huihao Xu ,  Steven Zier

    发明人： Hibourahima Camara ,  Louis Hsu ,  James Rockrohr ,  Karl Selander ,  Huihao Xu ,  Steven Zier

    IPC分类号： G05F1/10

    CPC分类号： H03K17/223 ,  G05F3/262 ,  G11C5/144 ,  G11C5/145 ,  G11C7/20 ,  H03K17/08

    摘要： A system for protecting a weak device operating in micro-electronic circuit that includes a high voltage power supply from high voltage overstressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.

    摘要翻译： 用于保护微电子电路中操作的弱电装置的系统包括来自高压过应力的高电压电源，防止在上电，掉电期间以及当多功率电源中的低电压电源时弱装置发生故障 供应系统不存在。 该系统包括低电压电源检测电路，其被配置为检测电路上电，电路掉电以及当低电压电源不存在时，并且在检测时产生控制信号。 该系统还包括被配置为提供涓流电流的受控电流镜装置，以响应于在电路加电，电路断电期间从低电压电源检测电路接收的控制信号来保持弱装置中的导通通道， 并且当低电压电源不存在时。

    Methods and apparatus for testing an integrated circuit
    4.
    发明申请
    Methods and apparatus for testing an integrated circuit 失效
    用于测试集成电路的方法和装置

    公开(公告)号：US20070103350A1

    公开(公告)日：2007-05-10

    申请号：US11272589

    申请日：2005-11-10

    申请人： Louis Hsu ,  Jack Mandelman ,  Joseph Marsh ,  Steven Zier

    发明人： Louis Hsu ,  Jack Mandelman ,  Joseph Marsh ,  Steven Zier

    IPC分类号： H03M1/10

    CPC分类号： H03M1/1076

    摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供一种测试模拟电路的方法。 该方法包括（1）向模拟电路提供一种适合于使模拟电路在测试期间像逻辑门一样起作用的屏蔽电路; 和（2）将数字信号施加到模拟电路以在晶片级测试模拟电路，以便检测模拟电路的一个或多个部件中的缺陷。 提供了许多其他方面。