-
公开(公告)号：US20060145751A1
公开(公告)日：2006-07-06
申请号：US10905436
申请日：2005-01-04
申请人： Gautam Gangasani , Louis Hsu , Karl Selander , Steven Zier
发明人： Gautam Gangasani , Louis Hsu , Karl Selander , Steven Zier
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET. A switching network is operable to controllably switch the first and second FETs and the third switching element between a powered on state in which the first and second currents are conducted and the third switching element is conducting, and a powered off state in which the first and second currents are not conducted and the third switching element is nonconducting such that the same drain to source voltage stress is applied to both first and second FETs.
摘要翻译： 提供电路和方法用于降低施加到FET的漏极/源极传导路径的电压应力和/或减小对可能具有薄栅极氧化物的FET的栅极氧化物的应力。 因此，在本文公开的电流镜电路中，第一场效应晶体管（FET）具有第一栅极和第一漏极，其中第一漏极导电连接到用于导电第一电流的电流源。 电流镜电路还包括具有导电连接到第一栅极的第二栅极的至少一个第二FET，其中第二FET可操作以输出与第一电流固定比例的第二电流。 具有第一导电端子的开关元件连接到第一栅极和第二栅极，第二导电端子连接到第一FET的第一漏极。 开关网络可操作以在第一和第二电流被导通的导通状态和第三开关元件导通之间可控地切换第一和第二FET和第三开关元件，以及断电状态，其中第一和第二开关 不传导第二电流，第三开关元件不导通，使得相同的漏极/源极电压应力施加到第一和第二FET。
-
公开(公告)号：US20070001736A1
公开(公告)日：2007-01-04
申请号：US11155848
申请日：2005-06-17
申请人： Herschel Ainspan , Gautam Gangasani , Louis Hsu , Jack Mandelman
发明人： Herschel Ainspan , Gautam Gangasani , Louis Hsu , Jack Mandelman
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： An apparatus and method for generating high-speed clock signals using a voltage-controlled-oscillator (VCO) device. The apparatus implements a linear variable gain amplifier rather than a non-linear hard limiter to remove unwanted signal modulation in VCO output signals. Implementation of the linear variable gain amplifier leads to the generation of amplitude modulation-free oscillation leading to the generation of jitter free high frequency clock signals.
-
公开(公告)号：US08599966B2
公开(公告)日：2013-12-03
申请号：US13173434
申请日：2011-06-30
CPC分类号： H03F3/45695 , H03F1/02 , H03G3/3089 , H04L25/0296
摘要： A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.
摘要翻译： 公开了一种数据接收器，操作数据接收器的方法和数据接收器中的集成耦合系统。 在一个实施例中，数据接收器包括用于接收输入数据信号的输入端，用于放大输入数据信号的选定分量的输入放大器和用于传输指定高频分量的输入信号路径和输入的基线分量 数据信号从输入端到输入放大器。 数据接收器还包括连接到输入端和输入放大器的前馈电阻网络。 该前馈电阻网络用于使用无源电阻网络将低频漂移补偿信号从输入端子转发到输入放大器，以补偿输入数据信号中的低频变化，并产生所需的偏置电压 在输入放大器。
-
4.发明授权System and method for latency reduction in speculative decision feedback equalizers 有权投机决策反馈均衡器延迟降低的系统和方法公开(公告)号：US08126045B2
公开(公告)日：2012-02-28
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。
-
公开(公告)号：US20130002347A1
公开(公告)日：2013-01-03
申请号：US13173434
申请日：2011-06-30
IPC分类号： H03G3/20
CPC分类号： H03F3/45695 , H03F1/02 , H03G3/3089 , H04L25/0296
摘要： A data receiver, a method of operating a data receiver, and an integrated coupling system in a data receiver are disclosed. In one embodiment, the data receiver comprises an input terminal for receiving an input data signal, an input amplifier for amplifying selected components of the input data signal, and an input signal path for transmitting specified high-frequency components and a baseline component of the input data signal from the input terminal to the input amplifier. The data receiver further comprises a feed-forward resistive network connected to the input terminal and to the input amplifier. This feed forward resistive network is used to forward a low-frequency drift compensation signal from the input terminal to the input amplifier, using a passive resistive network, to compensate for low frequency variations in the input data signal, and to develop a desired bias voltage at the input amplifier.
摘要翻译： 公开了一种数据接收器，操作数据接收器的方法和数据接收器中的集成耦合系统。 在一个实施例中，数据接收器包括用于接收输入数据信号的输入端，用于放大输入数据信号的选定分量的输入放大器和用于传输指定高频分量的输入信号路径和输入的基线分量 数据信号从输入端到输入放大器。 数据接收器还包括连接到输入端和输入放大器的前馈电阻网络。 该前馈电阻网络用于使用无源电阻网络将低频漂移补偿信号从输入端子转发到输入放大器，以补偿输入数据信号中的低频变化，并产生所需的偏置电压 在输入放大器。
-
公开(公告)号：US07394283B2
公开(公告)日：2008-07-01
申请号：US11467349
申请日：2006-08-25
IPC分类号： H03K17/16
CPC分类号： H03K19/018528
摘要： A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.
摘要翻译： 提供信号再生器，其包括共模参考发生器和信号转换器电路。 产生共模参考电压电平，其相对于用于制造共模参考发生器的工艺中的至少一个，提供给共模参考发生器的电源电压的电平或共模参考电压的温度可变 模式参考发生器运行。 信号转换器电路接收包括第一输入信号和第二输入信号的差分发送信号对，并输出表示由差分发送信号对承载的信息的单端输出信号。 使用来自共模参考发生器的反馈信号，反馈控制块根据共模参考电压电平控制单端输出信号的共模电平。
-
7.发明申请SYSTEM AND METHOD FOR LATENCY REDUCTION IN SPECULATIVE DECISION FEEDBACK EQUALIZERS 有权在决策反馈均衡器中减少衰减的系统和方法公开(公告)号：US20100054324A1
公开(公告)日：2010-03-04
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译： 决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。 检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。 门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。 选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。 再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。
-
公开(公告)号：US20080061825A1
公开(公告)日：2008-03-13
申请号：US11467349
申请日：2006-08-25
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.
摘要翻译： 提供信号再生器，其包括共模参考发生器和信号转换器电路。 产生共模参考电压电平，其相对于用于制造共模参考发生器的工艺中的至少一个，提供给共模参考发生器的电源电压的电平或共模参考电压的温度可变 模式参考发生器运行。 信号转换器电路接收包括第一输入信号和第二输入信号的差分发送信号对，并输出表示由差分发送信号对承载的信息的单端输出信号。 使用来自共模参考发生器的反馈信号，反馈控制块根据共模参考电压电平控制单端输出信号的共模电平。
-
公开(公告)号：US07205830B2
公开(公告)日：2007-04-17
申请号：US10905436
申请日：2005-01-04
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET. A switching network is operable to controllably switch the first and second FETs and the third switching element between a powered on state in which the first and second currents are conducted and the third switching element is conducting, and a powered off state in which the first and second currents are not conducted and the third switching element is nonconducting such that the same drain to source voltage stress is applied to both first and second FETs.
摘要翻译： 提供电路和方法用于降低施加到FET的漏极/源极传导路径的电压应力和/或减小对可能具有薄栅极氧化物的FET的栅极氧化物的应力。 因此，在本文公开的电流镜电路中，第一场效应晶体管（FET）具有第一栅极和第一漏极，其中第一漏极导电连接到用于导电第一电流的电流源。 电流镜电路还包括具有导电连接到第一栅极的第二栅极的至少一个第二FET，其中第二FET可操作以输出与第一电流固定比例的第二电流。 具有第一导电端子的开关元件连接到第一栅极和第二栅极，第二导电端子连接到第一FET的第一漏极。 开关网络可操作以在第一和第二电流被导通的导通状态和第三开关元件导通之间可控地切换第一和第二FET和第三开关元件，以及断电状态，其中第一和第二开关 不传导第二电流，第三开关元件不导通，使得相同的漏极/源极电压应力施加到第一和第二FET。
-
10.发明授权Variable-gain-amplifier based limiter to remove amplitude modulation from a VCO output 失效可变增益放大器的限幅器，用于从VCO输出中去除幅度调制公开(公告)号：US07205816B2
公开(公告)日：2007-04-17
申请号：US11155848
申请日：2005-06-17
CPC分类号： G06F1/04
摘要： An apparatus and method for generating high-speed clock signals using a voltage-controlled-oscillator (VCO) device. The apparatus implements a linear variable gain amplifier rather than a non-linear hard limiter to remove unwanted signal modulation in VCO output signals. Implementation of the linear variable gain amplifier leads to the generation of amplitude modulation-free oscillation leading to the generation of jitter free high frequency clock signals.
摘要翻译： 一种使用压控振荡器（VCO）装置产生高速时钟信号的装置和方法。 该装置实现线性可变增益放大器，而不是非线性硬限幅器，以消除VCO输出信号中不需要的信号调制。 线性可变增益放大器的实现导致无振幅调制的产生，导致产生无抖动的高频时钟信号。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.022 秒)
