公开(公告)号：US5953277A

公开(公告)日：1999-09-14

申请号：US037864

申请日：1998-03-10

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 用于向信号线21和22提供电荷的充电提供电路; 连接充电电路23和两条信号线21和22的第一连接电路24a和24b，以向两条信号线提供电荷; 以及通过第二控制信号将两条信号线21和22连接在一起的第二连接电路25，在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容的平均值之后，两条信号线断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5546342A

公开(公告)日：1996-08-13

申请号：US322543

申请日：1994-10-13

申请人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

发明人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

IPC分类号： G11C14/00 ,  G11C7/10 ,  G11C11/22 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

摘要翻译： 通过使用多个存储单元并减小施加到存储数据值“1”的存储单元的电介质膜的应力，可以延长半导体存储器件的寿命。 这通过减少保留存储数据所需的重写次数在本发明中实现。 具体地，本发明利用反向和重写装置在读取之后将数据反转并重写到存储器单元中，用于存储指示当前存储的数据是否处于反转状态的信号的存储装置，以及用于判断数据 应该反向输出。

公开(公告)号：US5828615A

公开(公告)日：1998-10-27

申请号：US785838

申请日：1997-01-08

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 电荷供给装置，用于向信号线21和22提供电荷; 连接充电提供电路23和两条信号线21和22的第一连接电路24a和24b，以向两条信号线提供电荷; 以及通过第二控制信号将两个信号线21和22连接在一起的第二连接电路25，并且在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容被平均后，两个信号线被断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5523974A

公开(公告)日：1996-06-04

申请号：US344680

申请日：1994-11-21

申请人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

IPC分类号： G11C11/401 ,  G11C11/22 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/789

摘要： A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

摘要翻译： 半导体存储器件包括主存储器单元，冗余存储器单元，冗余地址数据单元，其包括非易失性存储器，其电存储代替主存储单元中的故障存储器单元的冗余存储器单元的地址;控制器 电路15和冗余存储单元选择电路16.冗余存储单元选择电路用于保存从冗余地址数据单元读取的第一地址数据，并将第一地址数据与用于读或写的第二地址数据进行比较 通过控制电路输入的操作，从而选择主存储单元或冗余存储单元。

公开(公告)号：US06067265A

公开(公告)日：2000-05-23

申请号：US323894

申请日：1999-06-02

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 向信号线21和22提供电荷的充电器; 连接器24a和24b，连接充电提供器23和两个信号线21和22，以向两个信号线提供电荷; 以及通过第二控制信号将两个信号线21和22连接在一起的连接器25，并且在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容被平均后，两个信号线被断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5515312A

公开(公告)日：1996-05-07

申请号：US322541

申请日：1994-10-13

申请人： Tetsuji Nakakuma ,  Tatsumi Sumi ,  Hiroshige Hirano ,  George Nakane ,  Nobuyuki Moriwaki ,  Toshio Mukunoki

发明人： Tetsuji Nakakuma ,  Tatsumi Sumi ,  Hiroshige Hirano ,  George Nakane ,  Nobuyuki Moriwaki ,  Toshio Mukunoki

IPC分类号： G11C14/00 ,  G11C7/12 ,  G11C7/24 ,  G11C11/22 ,  G11C11/404

CPC分类号： G11C7/12 ,  G11C7/24

摘要： A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

摘要翻译： 一种半导体存储器件，包括一对位线，字线，单元板电极，连接到每个位线，字线和单元板电极的存储单元，以及仅允许预定数量的预防装置 读出存储在存储单元中的数据，之后数据被破坏并且随后的读出尝试不被检索。

公开(公告)号：US5751628A

公开(公告)日：1998-05-12

申请号：US700240

申请日：1996-08-20

申请人： Hiroshige Hirano ,  Nobuyuki Moriwaki ,  Tetsuji Nakakuma ,  Toshiyuki Honda ,  George Nakane

发明人： Hiroshige Hirano ,  Nobuyuki Moriwaki ,  Tetsuji Nakakuma ,  Toshiyuki Honda ,  George Nakane

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

摘要翻译： 存储单元包括铁电电容器，第一主存储单元连接到第一位线，第一参考存储单元连接到第二位线，第二主存储单元连接到第二位线，第二参考存储器 单元连接到第一位线。 当通过包括NAND门和NOR门的控制电路选择第一操作模式时，选择第一主存储单元和第一参考存储单元，并且当选择第二操作模式时，选择第一主存储单元和第二主存储单元 。 因此，通过切换两种操作模式之间的操作，提供了在低电压下稳定操作并且在高电压下高集成度的铁电存储器件。

公开(公告)号：US5467302A

公开(公告)日：1995-11-14

申请号：US354476

申请日：1994-12-12

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first ferrodielectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second ferrodielectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the ferrodielectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

摘要翻译： 位线BL0和/ BL0连接到读出放大器SA0，第一MOS晶体管的栅极连接到第一字线WL0，第一电介质电容器Cs1的第一电极到第一Qn的源极，第一 Qn至BL0，Cs1的第二电极到第一平板电极CP0，第二MOS晶体管Qn的栅极到第二字线DWL0，第二电介质电容器Cd2的第一电极到第二Qn的源极，漏极 的第二Qn至/ BL0的第二电极，以及Cd1的第二电极到第二平板电极DCP0，并且在关闭第二Qn之后，DCP0的逻辑电压反转。 因此，在采用强电介质元件的半导体存储器件中，虚拟存储电容器被可靠地初始化，并且能够在没有功耗集中的情况下实现高速读取。

公开(公告)号：US5392234A

公开(公告)日：1995-02-21

申请号：US161328

申请日：1993-12-02

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

IPC分类号： G11C11/22 ,  G11C13/00

CPC分类号： G11C11/22

摘要： Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first Ferroelectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second Ferroelectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the Ferroelectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

摘要翻译： 位线BL0和/ BL0连接到读出放大器SA0，第一MOS晶体管的栅极连接到第一字线WL0，第一铁电电容器Cs1的第一电极到第一Qn的源极，第一 Qn至BL0，Cs1的第二电极至第一平板电极CP0，第二MOS晶体管Qn的栅极至第二字线DWL0，第二铁电电容器Cd2的第一电极至第二Qn的源极，漏极 的第二Qn至/ BL0的第二电极，以及Cd1的第二电极到第二平板电极DCP0，并且在关闭第二Qn之后，DCP0的逻辑电压反转。 因此，在使用铁电元件的半导体存储器件中，虚拟存储电容器被可靠地初始化，并且能够在没有集中功耗的情况下实现高速读取。

公开(公告)号：US5675530A

公开(公告)日：1997-10-07

申请号：US691134

申请日：1996-08-01

申请人： Hiroshige Hirano ,  Nobuyuki Moriwaki ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Nobuyuki Moriwaki ,  Tatsumi Sumi

IPC分类号： G11C11/22 ,  G11C11/12

CPC分类号： G11C11/22

摘要： In a ferroelectric memory device comprising a ferroelectric capacitor as the memory cell capacitor, after applying a predetermined electric field to a main body memory cell capacitor C0 or C1 to conduct a writing operation, the electric field applied to the memory cell capacitor C0 or C1 is made zero. The operation is conducted so as not to apply an electric field on the ferroelectric capacitor. As a consequence, characteristic deterioration of the ferroelectric capacitor can be reduced to prevent the malfunction of the ferroelectric memory device.

摘要翻译： 在包含强电介质电容器作为存储单元电容器的铁电存储器件中，在将预定的电场施加到主体存储单元电容器C0或C1以进行写入操作之后，施加到存储单元电容器C0或C1的电场为 制成零。 进行操作，以便不对铁电电容器施加电场。 结果，可以降低铁电电容器的特性劣化，以防止铁电存储器件的故障。