公开(公告)号：US5751628A

公开(公告)日：1998-05-12

申请号：US700240

申请日：1996-08-20

申请人： Hiroshige Hirano ,  Nobuyuki Moriwaki ,  Tetsuji Nakakuma ,  Toshiyuki Honda ,  George Nakane

发明人： Hiroshige Hirano ,  Nobuyuki Moriwaki ,  Tetsuji Nakakuma ,  Toshiyuki Honda ,  George Nakane

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.

摘要翻译： 存储单元包括铁电电容器，第一主存储单元连接到第一位线，第一参考存储单元连接到第二位线，第二主存储单元连接到第二位线，第二参考存储器 单元连接到第一位线。 当通过包括NAND门和NOR门的控制电路选择第一操作模式时，选择第一主存储单元和第一参考存储单元，并且当选择第二操作模式时，选择第一主存储单元和第二主存储单元 。 因此，通过切换两种操作模式之间的操作，提供了在低电压下稳定操作并且在高电压下高集成度的铁电存储器件。

公开(公告)号：US5920509A

公开(公告)日：1999-07-06

申请号：US888307

申请日：1997-07-03

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3409 ,  G11C16/3404

摘要： By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.

摘要翻译： 通过将全部组反转控制栅极设置为逻辑电压“H”，存储单元阵列块的所有位线上的存储单元连接到反向电压供应电路，从而执行组反转操作。 当组反转控制门中的一个被设置为逻辑电压“H”时，具有偶数或奇数个存储单元阵列块的位线上的存储单元连接到反向电压供应电路，使得部分组 执行反转操作。 当列选择门之一被设置为逻辑电压“H”时，所选择的位线连接到反向电压供应电路。 因此，执行连接到所选位线的存储单元的线路反向操作。 因此，可以实现完全控制存储单元的截止电流的高速反转操作，并且可以通过改变用于执行反转操作的操作单元来实现低电压操作。

公开(公告)号：US5594697A

公开(公告)日：1997-01-14

申请号：US494827

申请日：1995-06-26

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C16/26

CPC分类号： G11C7/067 ,  G11C16/26 ,  G11C5/143 ,  G11C2207/063

摘要： A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

摘要翻译： 半导体器件包括非易失性存储单元和电流检测型读出放大器，用于检测流过存储单元的数据线的电流。 半导体器件还设置有用于当检测到的电源电压超过设定值时输出第一电压检测信号并在检测到的电源电压未超过设定值时输出第二电压检测信号的元件。 感测放大器包括用于响应于响应于第一电压检测信号的第二电压检测信号而将电源电压上的电平感测电流的相关特性切换到更高的元件。 因此，可以避免在应用低电源电压下可能导致来自存储单元的数据的错误读取。

公开(公告)号：US06872998B2

公开(公告)日：2005-03-29

申请号：US09333049

申请日：1999-06-15

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11502 ,  H01L28/55

摘要： A memory cell transistor using a word line WL as the gate thereof is provided in an active region OD, and a ferroelectric capacitor, including bottom electrode, ferroelectric film and top electrode TE, is formed on a field oxide film. A first interconnection layer is made up of storage lines, each connecting the top electrode TE to one of doped layers of the memory cell transistor, and bit lines, each of which is connected to the other doped layer. In a planar layout, the storage line-intersects only one side of the top electrode TE and the bit line BL does not overlap with the top electrode TE. Thus, it is possible to prevent the retention characteristics of the ferroelectric capacitor from being deteriorated due to the stress applied by the first interconnection layer to the ferroelectric capacitor. As a result, the reliability of a ferroelectric memory device, including, in a memory cell, a ferroelectric capacitor with a ferroelectric film interposed between the bottom and top electrodes, can be improved.

摘要翻译： 使用字线WL作为其栅极的存储单元晶体管设置在有源区域OD中，并且在场氧化膜上形成包括底电极，铁电体膜和顶电极TE的铁电电容器。 第一互连层由存储线组成，每个存储线将顶部电极TE连接到存储单元晶体管的一个掺杂层，以及位线，每个位线连接到另一个掺杂层。 在平面布局中，存储线仅与顶部电极TE的一侧相交，并且位线BL不与顶部电极TE重叠。 因此，可以防止由于第一互连层向强电介质电容器施加的应力而使铁电电容器的保持特性劣化。 结果，可以提高包括在存储单元中的强电介质存储器件的可靠性，该铁电电容器具有置于底部和顶部电极之间的铁电体膜。

公开(公告)号：US5841698A

公开(公告)日：1998-11-24

申请号：US697511

申请日：1996-08-26

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C16/26 ,  G11C16/06

CPC分类号： G11C7/067 ,  G11C16/26 ,  G11C5/143 ,  G11C2207/063

摘要： A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

摘要翻译： 半导体器件包括非易失性存储单元和电流检测型读出放大器，用于检测流过存储单元的数据线的电流。 半导体器件还设置有用于当检测到的电源电压超过设定值时输出第一电压检测信号并在检测到的电源电压未超过设定值时输出第二电压检测信号的元件。 感测放大器包括用于响应于响应于第一电压检测信号的第二电压检测信号而将电源电压上的电平感测电流的相关特性切换到更高的元件。 因此，可以避免在应用低电源电压下可能导致来自存储单元的数据的错误读取。

公开(公告)号：US5831904A

公开(公告)日：1998-11-03

申请号：US690790

申请日：1996-08-01

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3409 ,  G11C16/3404

摘要： By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.

摘要翻译： 通过将全部组反转控制栅极设置为逻辑电压“H”，存储单元阵列块的所有位线上的存储单元连接到反向电压供应电路，从而执行组反转操作。 当组反转控制门中的一个被设置为逻辑电压“H”时，具有偶数或奇数个存储单元阵列块的位线上的存储单元连接到反向电压供应电路，使得部分组 执行反转操作。 当列选择门之一被设置为逻辑电压“H”时，所选择的位线连接到反向电压供应电路。 因此，执行连接到所选位线的存储单元的线路反向操作。 因此，可以实现完全控制存储单元的截止电流的高速反转操作，并且可以通过改变用于执行反转操作的操作单元来实现低电压操作。

公开(公告)号：US5687126A

公开(公告)日：1997-11-11

申请号：US697507

申请日：1996-08-26

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C16/26

CPC分类号： G11C7/067 ,  G11C16/26 ,  G11C5/143 ,  G11C2207/063

摘要： A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

公开(公告)号：US06081036A

公开(公告)日：2000-06-27

申请号：US973891

申请日：1998-03-09

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： H01L21/02 ,  H01L23/528 ,  H01L23/535

CPC分类号： H01L28/55 ,  H01L28/60

摘要： A semiconductor device is provided wich includes a first wiring and second wirings in which end portions of the second wirings connected to the first wiring are bent parallel to that forms a predetermined angle with respect to the first direction. The first wiring extends along a first direction and has a wiring width direction in a second direction perpendicular to the first direction, where stresses are generated inside. The second wirings are situated above the first wiring, connected to the first wiring through a contact hole, and affected by the stresses of the first wiring.

摘要翻译： PCT No.PCT / JP97 / 01346 Sec。 371日期1998年3月9日 102（e）1998年3月9日PCT 1997年4月18日PCT PCT。 出版物WO97 / 40528 日期：1997年10月30日提供了一种半导体器件，其包括第一布线和第二布线，其中连接到第一布线的第二布线的端部弯曲成平行的第二布线相对于第一布线形成预定角度。 第一布线沿着第一方向延伸，并且在垂直于第一方向的第二方向上具有布线宽度方向，内部产生应力。 第二布线位于第一布线的上方，通过接触孔连接到第一布线，并受到第一布线的应力的影响。

公开(公告)号：US5706242A

公开(公告)日：1998-01-06

申请号：US697508

申请日：1996-08-26

申请人： Hiroshige Hirano ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Toshiyuki Honda

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C16/26 ,  G05F1/40

CPC分类号： G11C7/067 ,  G11C16/26 ,  G11C5/143 ,  G11C2207/063

摘要： A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be a higher response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

摘要翻译： 半导体器件包括非易失性存储单元和电流检测型读出放大器，用于检测流过存储单元的数据线的电流。 半导体器件还设置有用于当检测到的电源电压超过设定值时输出第一电压检测信号并在检测到的电源电压未超过设定值时输出第二电压检测信号的元件。 感测放大器包括用于在电源电压上切换电平感测电流的相关特性以对第一电压检测信号作出较高响应的元件。 因此，可以避免在应用低电源电压下可能导致来自存储单元的数据的错误读取。

公开(公告)号：US5760606A

公开(公告)日：1998-06-02

申请号：US633683

申请日：1996-04-17

申请人： Hiroshige Hirano ,  Shigeo Chaya ,  Toshiyuki Honda

发明人： Hiroshige Hirano ,  Shigeo Chaya ,  Toshiyuki Honda

IPC分类号： H03K3/356 ,  H03K17/0416 ,  H03K17/10 ,  H03K19/0185

CPC分类号： H03K3/356147 ,  H03K17/04163 ,  H03K17/102 ,  H03K3/356052

摘要： A switch circuit having a high withstanding voltage and low driving ability and another switch circuit having a low withstanding voltage and high driving ability are connected to a specified node in parallel. When discharging the charges of the specified node, the switch circuit having the high withstanding voltage is turned ON and the switch circuit having the great driving ability is then turned ON. Accordingly, it is sufficient that only the transition of the logical voltage of a switch circuit having the high withstanding voltage is taken into consideration to set the ON timing of a switch circuit having the high driving ability. Consequently, timing setting can be performed easily. After the switch circuit having the high driving ability is turned ON, a discharge path for the charges of the specified node takes two paths which passes through both switch circuits in parallel. Consequently, an operating speed can be increased.

摘要翻译： 具有高耐受电压和低驱动能力的开关电路以及具有低耐压和高驱动能力的另一开关电路并联连接到指定节点。 当放电指定节点的电荷时，具有高耐受电压的开关电路导通，并且具有较大驱动能力的开关电路然后导通。 因此，仅考虑具有高耐受电压的开关电路的逻辑电压的转变，以设定具有高驱动能力的开关电路的导通定时就足够了。 因此，可以容易地进行定时设定。 在具有高驱动能力的开关电路被接通之后，用于指定节点的电荷的放电路径需要并行通过两个开关电路的两条路径。 因此，可以提高运转速度。