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    Dependency checking and forwarding of variable width operands
    2.
    发明授权
    Dependency checking and forwarding of variable width operands 失效
    可变宽度操作数的依赖关系检查和转发

    公开(公告)号：US5590352A

    公开(公告)日：1996-12-31

    申请号：US233567

    申请日：1994-04-26

    申请人： Gerald D. Zuraski, Jr. ,  Scott A. White ,  Murali S. Chinnakonda ,  David S. Christie

    发明人： Gerald D. Zuraski, Jr. ,  Scott A. White ,  Murali S. Chinnakonda ,  David S. Christie

    IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

    CPC分类号： G06F9/30043 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30192 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.

    摘要翻译： 使用可变位宽的操作数数据执行操作的流水线或超标量处理器（10）通过将固定位宽操作数（200）划分成几个部分操作数字段（215,216和217）来提高并行性能，并且检查数据依赖性， 在这些字段中标记和转发数据，彼此独立。 指令解码器（18）同时将多个ROP调度到各种功能单元（20,21,22和80）。 通过注册重命名来解决与注册资源有关的冲突。 然而，当寄存器结构重叠时，实现寄存器重命名是困难的。 本发明支持对寄存器操作数的部分位字段的独立依赖性检查，标记和转发，其组合允许寄存器重命名。 因此，可变宽度寄存器操作数结构大大有助于处理器解决数据依赖性。 操作数由重排序缓冲器（26）标记，并在数据可用时提供数据，而不考虑数据类型。 这种依赖关系的方法支持并行的操作性能，并提供整体处理速度的实质性改进。 因此，处理器促进对重叠的数据结构起作用的操作的并行处理，否则其将抵抗并行处理。

    Memory system for supporting multiple parallel accesses at very high frequencies
    5.
    发明授权
    Memory system for supporting multiple parallel accesses at very high frequencies 有权
    用于以非常高的频率支持多个并行访问的存储器系统

    公开(公告)号：US06963962B2

    公开(公告)日：2005-11-08

    申请号：US10120686

    申请日：2002-04-11

    申请人： Hebbalalu S. Ramagopal ,  Murali S. Chinnakonda ,  Thang M. Tran

    发明人： Hebbalalu S. Ramagopal ,  Murali S. Chinnakonda ,  Thang M. Tran

    IPC分类号： G06F13/16 ,  G11C7/10 ,  G06F12/00

    CPC分类号： G11C7/10 ,  G06F13/1615 ,  G06F13/1647

    摘要： A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a memory control unit for processing access requests from the processor, from the store buffer and from the load buffer. The memory control unit may include prioritization logic for selecting access requests in accordance with a priority scheme and bank conflict logic for detecting and handling conflicts between access requests. The pipelined memory may be configured to output two load results per clock cycle at very high speed.

    摘要翻译： 用于与处理器（例如数字信号处理器）一起操作的存储器系统包括高速流水线存储器，用于保存来自处理器的存储访问请求的存储缓冲器，用于保存来自处理器的加载访问请求的加载缓冲器和存储器 控制单元，用于处理来自处理器，存储缓冲器和加载缓冲器的访问请求。 存储器控制单元可以包括用于根据优先级方案选择访问请求的优先化逻辑和用于检测和处理访问请求之间的冲突的库冲突逻辑。 流水线存储器可以被配置为以非常高的速度在每个时钟周期输出两个负载结果。

    Method and apparatus for fast dependency coordinate matching
    6.
    发明授权
    Method and apparatus for fast dependency coordinate matching 失效
    快速依赖性坐标匹配的方法和装置

    公开(公告)号：US06889314B2

    公开(公告)日：2005-05-03

    申请号：US09965211

    申请日：2001-09-26

    申请人： Nicholas G. Samra ,  Murali S. Chinnakonda

    发明人： Nicholas G. Samra ,  Murali S. Chinnakonda

    IPC分类号： G06F9/38 ,  G06F9/52

    CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/384

    摘要： Disclosed herein is a method for matching dependency coordinates and an efficient apparatus for performing the dependency coordinate matching very quickly. A plurality of buffers to store instructions is set forth. Each storage location of a buffer corresponds to a particular pair of dependency coordinates. Dependency matching logic receives the dependency coordinates for a buffered instruction and scheduling information pertaining to dispatched instructions. The dependency matching logic indicates whether a dependency precludes scheduling of the corresponding buffered instruction. Dependency checking logic produces a ready signal for the buffered instruction when no such dependency is indicated by the dependency matching logic.

    摘要翻译： 这里公开了一种用于匹配依赖性坐标的方法和用于非常快速地执行依赖性坐标匹配的有效装置。 阐述存储指令的多个缓冲器。 缓冲器的每个存储位置对应于一对特定的依赖性坐标。 依赖性匹配逻辑接收缓冲指令的依赖性坐标和与调度指令有关的调度信息。 依赖性匹配逻辑指示依赖性是否排除对相应缓存指令的调度。 当依赖性匹配逻辑不指示这种依赖性时，依赖性检查逻辑为缓冲指令产生就绪信号。