摘要:
Circuit arrangement having a chip card controller with connections which can be used to access the chip card controller in accordance with the ISO standard and which are connected or can be connected to an ISO interface. The connections include at least one first connection, which can be connected to the ISO interface via a switch device. In addition, the circuit arrangement includes a further controller with at least one controller connection which is coupled to the switch device such that the first connection of the chip card controller can be connected to the controller connection via the switch device. The switch device can be switched between a first and a second state, where in the first state the first connection of the chip card controller is decoupled from the controller connection and is connected to the ISO interface, and where in the second state the first connection of the chip card controller is decoupled from the ISO interface and is connected to the controller connection.
摘要:
Circuit arrangement having a chip card controller with connections which can be used to access the chip card controller in accordance with the ISO standard and which are connected or can be connected to an ISO interface. The connections include at least one first connection, which can be connected to the ISO interface via a switch device. In addition, the circuit arrangement includes a further controller with at least one controller connection which is coupled to the switch device such that the first connection of the chip card controller can be connected to the controller connection via the switch device. The switch device can be switched between a first and a second state, where in the first state the first connection of the chip card controller is decoupled from the controller connection and is connected to the ISO interface, and where in the second state the first connection of the chip card controller is decoupled from the ISO interface and is connected to the controller connection.
摘要:
One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.
摘要:
A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.
摘要:
Apparatus for contactless data transmission according to a predetermined transmission protocol providing control information and payload for a data transmission, with a near field communicator and an interface connected to the near field communicator, the interface being operative to exchange, using a first protocol, data with the near field communicator for the contactless transmission. In this context, the first protocol provides a transmission of control information and payload, the payload of the first protocol including the control information and the payload of the predetermined protocol. The apparatus further includes a module coupled to the interface and being operative to exchange, using the payload of the first protocol, the control information and the payload of the predetermined transmission protocol for the data exchanged contactlessly by the near field communicator.
摘要:
A parallel data bus having a plurality of bus lines, and a bus mode switching device for switching between data transmission at a high data transmission rate and data transmission at high data integrity.
摘要:
An encryption unit and decryption unit located in an encryption/decryption device may be used both for encryption and decryption, without their effects canceling each other out when, between the decryption input of the decrypter and the encryption output of the encrypter. An encryption combiner maps the encryption result data block at the encryption output to a mapped encryption result data block according to an encryption combining mapping and is exemplarily used when encrypting. A decryption combiner maps the encryption result data block at the encryption output to an inversely mapped encryption result data block according to a decryption combining mapping which is inverse to the encryption combining mapping and is exemplarily used when decrypting.
摘要:
A pseudorandom number generator includes a first elemental shift register having a non-linear feedback feature, a second elemental shift register and combiner for combining signals at an output of the first elemental shift register and the second elemental shift register to obtain a combined signal representing a pseudorandom number. The combination of individual non-linear elemental shift registers allows a safe and flexible implementation of random number generators, the output sequences of which include a high linear complexity and a high period length.
摘要:
One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.
摘要:
An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.