METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS
    1.
    发明申请
    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS 审中-公开
    用氧化铝/氮化物层生产粘结的结构的方法

    公开(公告)号:US20110180896A1

    公开(公告)日:2011-07-28

    申请号:US12692983

    申请日:2010-01-25

    IPC分类号: H01L29/06 H01L21/762

    CPC分类号: H01L21/76256

    摘要: A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

    摘要翻译: 形成接合晶片结构的方法包括:在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。 或者,可以在接合之前在氮化硅层上形成第三氧化硅层。 然后在第一和第三氧化硅层之间形成键合界面。 还提供了通过这种方法形成的接合晶片结构。

    Asymmetric epitaxy and application thereof
    8.
    发明授权
    Asymmetric epitaxy and application thereof 有权
    不对称外延及其应用

    公开(公告)号:US08198673B2

    公开(公告)日:2012-06-12

    申请号:US13080702

    申请日:2011-04-06

    IPC分类号: H01L21/00

    摘要: The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.

    摘要翻译: 本发明提供了形成非对称场效应晶体管的方法。 该方法包括在半导体衬底的顶部上形成栅极结构,该栅极结构包括一个栅极叠层和邻近该栅极叠层的侧壁的间隔物,并具有与第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入,从而形成与第一侧相邻的离子注入区域,其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果,在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。

    Fabrication of Field Effect Devices Using Spacers
    9.
    发明申请
    Fabrication of Field Effect Devices Using Spacers 失效
    使用Spacers制造场效应器件

    公开(公告)号:US20110171788A1

    公开(公告)日:2011-07-14

    申请号:US12684997

    申请日:2010-01-11

    IPC分类号: H01L21/336

    摘要: A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

    摘要翻译: 一种形成场效应器件的方法包括在绝缘体上硅层(SOI)上形成栅极部分,在邻近栅极部分的SOI层上形成第一间隔元件,在SOI层上沉积间隔物材料层, 第一隔离构件和栅极部分,去除间隔物材料层的部分,以在与第一间隔件相邻的SOI层上形成第二间隔件,通过将离子注入到SOI层上形成源极区域和漏极区域 SOI层,并蚀刻以除去第二间隔件。

    Buried stress isolation for high-performance CMOS technology
    10.
    发明申请
    Buried stress isolation for high-performance CMOS technology 失效
    埋地应力隔离用于高性能CMOS技术

    公开(公告)号:US20070020867A1

    公开(公告)日:2007-01-25

    申请号:US11183062

    申请日:2005-07-15

    IPC分类号: H01L21/336

    摘要: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.

    摘要翻译: 场效应晶体管(FET)包括衬底; 在衬底上的掩埋氧化物(BOX)层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域,其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极,其中所述高应力膜适于在所述电流通道区域中产生机械应力,其中所述高应力膜适于拉伸所述电流通道区域,以便产生机械应力 当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力,并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。