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    SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC
    4.
    发明申请
    SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC 审中-公开
    SOI结构包括一个BURIED BORON NITRIDE DIELECTRIC

    公开(公告)号：US20130196483A1

    公开(公告)日：2013-08-01

    申请号：US13604004

    申请日：2012-09-05

    申请人： Robert H. Dennard ,  Alfred Grill ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dea-Gyu Park ,  Ghavam G. Shahidi ,  Leathen Shi

    发明人： Robert H. Dennard ,  Alfred Grill ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dea-Gyu Park ,  Ghavam G. Shahidi ,  Leathen Shi

    IPC分类号： H01L21/30

    CPC分类号： H01L29/78603 ,  H01L21/02112 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76254

    摘要： Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.

    摘要翻译： 氮化硼被用作包括SOI层和手柄衬底的SOI结构的掩埋电介质。 氮化硼位于SOI层和手柄基板之间。 氮化硼具有接近二氧化硅的介电常数和热膨胀系数。 然而，氮化硼具有比二氧化硅好得多的湿润以及耐干蚀刻性。 在SOI结构中，在多次湿和干蚀刻期间氮化硼的材料损失减少，使得形貌和/或桥接不是器件集成的障碍。 氮化硼具有低介电常数，使得内置在SOI有源区中的器件不会带来充电效应。

    Adaptive chuck for planar bonding between substrates
    5.
    发明授权
    Adaptive chuck for planar bonding between substrates 失效
    用于基板之间的平面粘合的自适应卡盘

    公开(公告)号：US08408262B2

    公开(公告)日：2013-04-02

    申请号：US12575968

    申请日：2009-10-08

    申请人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

    发明人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

    IPC分类号： B32B41/00

    CPC分类号： H01L21/6833 ,  B32B37/0007 ,  B32B2457/14 ,  Y10T156/1002

    摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.

    摘要翻译： 静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。 独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。 可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。

    LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
    6.
    发明申请
    LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 有权
    具有后续自对准的双盒式背盖的低成本制造硅绝缘体波纹

    公开(公告)号：US20120112309A1

    公开(公告)日：2012-05-10

    申请号：US13350889

    申请日：2012-01-16

    申请人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

    发明人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/76275 ,  H01L21/76283 ,  H01L27/1203

    摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.

    摘要翻译： 用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。 还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

    Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
    8.
    发明授权
    Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
    拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）

    公开(公告)号：US07485518B2

    公开(公告)日：2009-02-03

    申请号：US11684855

    申请日：2007-03-12

    申请人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

    发明人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

    摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

    摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

    MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE
    10.
    发明申请
    MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
    多层和单层平面定向半导体基板

    公开(公告)号：US20080099844A1

    公开(公告)日：2008-05-01

    申请号：US11969320

    申请日：2008-01-04

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

    IPC分类号： H01L29/786

    CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/823807 ,  H01L27/1203

    摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

    摘要翻译： 绝缘体上半导体衬底及其制造方法。 所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向， 第一晶体方向与第二晶体方向不同。