公开(公告)号：US20090252210A1

公开(公告)日：2009-10-08

申请号：US12370702

申请日：2009-02-13

申请人： Thilo Rubehn ,  Joachim Ritter ,  Gert Umbach ,  Dieter Baecher ,  Wolfgang Horn ,  Joerg Franke

发明人： Thilo Rubehn ,  Joachim Ritter ,  Gert Umbach ,  Dieter Baecher ,  Wolfgang Horn ,  Joerg Franke

IPC分类号： H04B17/00 ,  H04L27/00

CPC分类号： G01R31/31713 ,  G01R31/31726

摘要： The invention relates to an integrated circuit arrangement with connection contacts for the serial exchange of data and/or signals with external components and apparatuses and with a control apparatus and/or a serial interface for the clocked receiving of data by means of a signal voltage on such a connection contact, which voltage is modulated between at least one low, one middle and one high voltage state. The control apparatus and/or the interface are designed in such a manner that data is sent in a sending mode via the connection contact in that the switching apparatus, after having received a slope changing in particular from the middle voltage state into in particular the higher or the lower voltage state, pulls the voltage state into the in particular opposite lower or higher voltage state. Furthermore, the invention relates to an apparatus and a process for operating such a circuit arrangement.

摘要翻译： 本发明涉及一种具有连接触点的集成电路装置，用于与外部组件和装置的数据和/或信号串行交换，并具有控制装置和/或串行接口，用于通过信号电压在时钟上接收数据 这种连接接点，该电压在至少一个低电压，一个中间电压和一个高电压状态之间被调制。 控制装置和/或接口被设计成在接收到特别是从中间电压状态变化的斜率特别是更高的数据之后，经由连接触点以发送模式发送数据，因为开关装置 或较低电压状态，将电压状态拉至特别相反的较低或较高电压状态。 此外，本发明涉及一种用于操作这种电路装置的装置和方法。

公开(公告)号：US07728624B2

公开(公告)日：2010-06-01

申请号：US11546011

申请日：2006-10-10

申请人： Gert Umbach

发明人： Gert Umbach

IPC分类号： H03K19/094 ,  G06F7/38 ,  H03K19/173 ,  H01L25/00 ,  H03K19/00 ,  G06F7/44

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly on the input side of this selection unit. The first selection units are coupled to each other such that a horizontal and/or vertical logical interconnection of the arithmetic/logic units within a group, and/or a logical interconnection of arithmetic/logic units to an upstream group can be implemented. Second selection units are in each case connected on the output side of a column of arithmetic/logic units. The second selection units of a group are connected on the output side to one bus each, and a microprocessor is coupled to this bus.

摘要翻译： 一种包括至少一个组的集成电路，包括以子组布置的多个算术/逻辑单元。 在多个算术/逻辑单元的输入处的子组中，在每种情况下，第一选择单元中的单个单元连接在输入侧，其中没有其他选择单元直接连接在该选择单元的输入侧。 第一选择单元彼此耦合，使得可以实现组内的算术/逻辑单元和/或算术/逻辑单元与上游组的逻辑互连的水平和/或垂直逻辑互连。 在每种情况下，第二选择单元连接在算术/逻辑单元列的输出侧。 组的第二选择单元在输出侧连接到每个一个总线，并且微处理器耦合到该总线。

公开(公告)号：US20070080713A1

公开(公告)日：2007-04-12

申请号：US11546011

申请日：2006-10-10

申请人： Gert Umbach

发明人： Gert Umbach

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17732

摘要： An integrated circuit comprising at least one group comprising having multiple arithmetic/logic units arranged in sub-groups. In the sub-groups at inputs of multiple arithmetic/logic units, in each case a single one of the first selection units is connected on the input side, wherein no other selection unit is connected directly on the input side of this selection unit. The first selection units are coupled to each other such that a horizontal and/or vertical logical interconnection of the arithmetic/logic units within a group, and/or a logical interconnection of arithmetic/logic units to an upstream group can be implemented. Second selection units are in each case connected on the output side of a column of arithmetic/logic units. The second selection units of a group are connected on the output side to one bus each, and a microprocessor is coupled to this bus.

摘要翻译： 一种包括至少一个组的集成电路，包括以子组布置的多个算术/逻辑单元。 在多个算术/逻辑单元的输入处的子组中，在每种情况下，第一选择单元中的单个单元连接在输入侧，其中没有其他选择单元直接连接在该选择单元的输入侧。 第一选择单元彼此耦合，使得可以实现组内的算术/逻辑单元和/或算术/逻辑单元与上游组的逻辑互连的水平和/或垂直逻辑互连。 在每种情况下，第二选择单元连接在算术/逻辑单元列的输出侧。 组的第二选择单元在输出侧连接到每个一个总线，并且微处理器耦合到该总线。

公开(公告)号：US08594225B2

公开(公告)日：2013-11-26

申请号：US12370702

申请日：2009-02-13

申请人： Thilo Rubehn ,  Joachim Ritter ,  Gert Umbach ,  Dieter Baecher ,  Wolfgang Horn ,  Joerg Franke

发明人： Thilo Rubehn ,  Joachim Ritter ,  Gert Umbach ,  Dieter Baecher ,  Wolfgang Horn ,  Joerg Franke

IPC分类号： H04L27/00

CPC分类号： G01R31/31713 ,  G01R31/31726

摘要： The invention relates to an integrated circuit arrangement with connection contacts for the serial exchange of data and/or signals with external components and apparatuses and with a control apparatus and/or a serial interface for the clocked receiving of data by means of a signal voltage on such a connection contact, which voltage is modulated between at least one low, one middle and one high voltage state. The control apparatus and/or the interface are designed in such a manner that data is sent in a sending mode via the connection contact in that the switching apparatus, after having received a slope changing in particular from the middle voltage state into in particular the higher or the lower voltage state, pulls the voltage state into the in particular opposite lower or higher voltage state. Furthermore, the invention relates to an apparatus and a process for operating such a circuit arrangement.

摘要翻译： 本发明涉及一种具有连接触点的集成电路装置，用于与外部组件和装置的数据和/或信号串行交换，并具有控制装置和/或串行接口，用于通过信号电压在时钟上接收数据 这种连接接点，该电压在至少一个低电压，一个中间电压和一个高电压状态之间被调制。 控制装置和/或接口被设计成在接收到特别是从中间电压状态变化的斜率特别是更高的数据之后，经由连接触点以发送模式发送数据，因为开关装置 或较低电压状态，将电压状态拉至特别相反的较低或较高电压状态。 此外，本发明涉及一种用于操作这种电路装置的装置和方法。

公开(公告)号：US06826648B1

公开(公告)日：2004-11-30

申请号：US09664644

申请日：2000-09-19

申请人： Gert Umbach

发明人： Gert Umbach

IPC分类号： G06F1200

CPC分类号： G06F13/1689

摘要： A storage control for implementing switching commands for access to storage cells for writing or reading data receives control commands which are allocated to the data. The storage control has a command set for at least one memory type with command sequences of individual switch commands to be processed in a predetermined succession, which are activated by the control commands one after another at a predetermined time after the activation of the preceding switch command. Here, depending on the previous switch command and the current control command, there is created an activation command, which activates the current switch command. Moreover, the storage control contains information items allocated to the storage cells which indicate the predetermined time for the respective switch command.

摘要翻译： 用于实现用于访问用于写入或读取数据的存储单元的切换命令的存储控制接收分配给数据的控制命令。 存储控制具有用于至少一个存储器类型的命令集，其具有将以预定的顺序处理的各个开关命令的命令序列，这些命令序列在激活前一个开关命令之后的预定时间由控制命令一个接一个地激活 。 这里，根据以前的切换命令和当前的控制命令，创建一个激活当前切换命令的激活命令。 此外，存储控制包含分配给存储单元的指示相应开关命令的预定时间的信息项。