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    Multidimensional switch network
    2.
    发明授权
    Multidimensional switch network 失效
    多维交换机网络

    公开(公告)号：US07486619B2

    公开(公告)日：2009-02-03

    申请号：US10793068

    申请日：2004-03-04

    申请人： Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas ,  Matthias Augustin Blumrich

    发明人： Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas ,  Matthias Augustin Blumrich

    IPC分类号： H04L12/28

    CPC分类号： H04L49/1576 ,  H04L45/06

    摘要： Multidimensional switch data networks are disclosed, such as are used by a distributed-memory parallel computer, as applied for example to computations in the field of life sciences. A distributed memory parallel computing system comprises a number of parallel compute nodes and a message passing data network connecting the compute nodes together. The data network connecting the compute nodes comprises a multidimensional switch data network of compute nodes having N dimensions, and a number/array of compute nodes Ln in each of the N dimensions. Each compute node includes an N port routing element having a port for each of the N dimensions. Each compute node of an array of Ln compute nodes in each of the N dimensions connects through a port of its routing element to an Ln port crossbar switch having Ln ports. Several embodiments are disclosed of a 4 dimensional computing system having 65,536 compute nodes.

    摘要翻译： 公开了多维交换机数据网络，例如由分布式存储器并行计算机使用的，例如应用于生命科学领域的计算。 分布式存储器并行计算系统包括多个并行计算节点和将计算节点连接在一起的消息传递数据网络。 连接计算节点的数据网络包括具有N维的计算节点的多维交换机数据网络和N个维度中的每一个中的计算节点Ln的数量/数组。 每个计算节点包括具有用于N个维度中的每一个的端口的N端口路由元件。 每个N维中的Ln计算节点阵列的每个计算节点通过其路由元素的端口连接到具有Ln端口的Ln端口交叉开关。 公开了具有65,536个计算节点的四维计算系统的几个实施例。

    Direct Memory Access Transfer Completion Notification
    3.
    发明申请
    Direct Memory Access Transfer Completion Notification 失效
    直接内存访问传输完成通知

    公开(公告)号：US20080307121A1

    公开(公告)日：2008-12-11

    申请号：US11758167

    申请日：2007-06-05

    申请人： Dong Chen ,  Mark E. Giampapa ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker ,  Burkhard D. Steinmacher-Burow ,  Pavlos Vranas

    发明人： Dong Chen ,  Mark E. Giampapa ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker ,  Burkhard D. Steinmacher-Burow ,  Pavlos Vranas

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

    摘要翻译： 提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。 实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器 依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

    Direct memory access transfer completion notification
    4.
    发明授权
    Direct memory access transfer completion notification 失效
    直接内存访问传输完成通知

    公开(公告)号：US07765337B2

    公开(公告)日：2010-07-27

    申请号：US11758167

    申请日：2007-06-05

    申请人： Dong Chen ,  Mark E. Giampapa ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker ,  Burkhard D. Steinmacher-Burow ,  Pavlos Vranas

    发明人： Dong Chen ,  Mark E. Giampapa ,  Philip Heidelberger ,  Sameer Kumar ,  Jeffrey J. Parker ,  Burkhard D. Steinmacher-Burow ,  Pavlos Vranas

    IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F13/00

    CPC分类号： G06F13/28

    摘要： Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.

    摘要翻译： 提供方法，计算节点和计算机程序产品用于直接内存访问（“DMA”）传输完成通知。 实施例包括通过原始计算节点上的原始DMA引擎确定要发送到目标计算节点的应用消息的数据描述符当前是否处于先进先出先入先出（FIFO）缓冲器 依赖于先前与数据描述符相关联的序列号，当前在注入FIFO缓冲器中的描述符的总数以及存储在注入FIFO缓冲器中的最新数据描述符的当前序列号; 并且如果消息的数据描述符当前不在注入FIFO缓冲器中，则通知源DMA引擎上的处理器核心消息已被发送。

    Collective network for computer structures
    6.
    发明授权
    Collective network for computer structures 有权
    计算机结构集体网络

    公开(公告)号：US08001280B2

    公开(公告)日：2011-08-16

    申请号：US11572372

    申请日：2005-07-18

    申请人： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

    发明人： Matthias A. Blumrich ,  Paul W. Coteus ,  Dong Chen ,  Alan Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Todd E. Takken ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

    IPC分类号： G06F15/16

    CPC分类号： G06F15/17381 ,  H04L1/1845 ,  H04L12/4641

    摘要： A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices ate included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

    摘要翻译： 一种用于实现互连处理节点之间的高速，低延迟全局集体通信的系统和方法。 全局集体网络最优地使得能够在具有多个互连处理节点的计算机结构中执行并行算法操作期间执行集体缩减操作。 路由器设备包括通过链路互连网络的节点，以便于在虚拟网络和类结构的节点处执行低延迟全局处理操作。 全局集体网络可以被配置为以异步或同步方式提供全局屏障和中断功能。 当在大规模并行超级计算结构中实现时，全局集体网络根据处理算法的需要在物理上和逻辑上可分割。

    Deterministic error recovery protocol
    9.
    发明授权
    Deterministic error recovery protocol 失效
    确定性错误恢复协议

    公开(公告)号：US07149920B2

    公开(公告)日：2006-12-12

    申请号：US10674952

    申请日：2003-09-30

    申请人： Matthew A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

    发明人： Matthew A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Burkhard D. Steinmacher-Burow ,  Pavlos M. Vranas

    IPC分类号： G06F11/00 ,  G06F11/07

    CPC分类号： G06F11/1443 ,  G06F11/0709 ,  G06F11/0793 ,  H04L1/0052 ,  H04L69/28 ,  H04L69/40 ,  H04L2001/0092

    摘要： Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.

    摘要翻译： 公开了一种用于与具有第一和第二节点的通信系统一起使用的错误恢复方法和系统，每个所述节点具有接收器和发送器，第一节点的发送器通过第一电缆连接到第二节点的接收器 并且第二节点的发送者通过第二电缆连接到第一节点的接收器。 所述方法包括在所述节点中的一个检测到错误之后的两个节点进入相同的定义状态的步骤。 特别地，第一节点的接收机进入错误状态，在定义的时间段T内保持在错误状态，并且在所述定义的时间段T之后进入等待状态。 此外，第一节点的发送方在给定的时间段Te的情况下向第二节点的接收者发送错误消息，并且在定义的时间段Te之后，第一节点的发送者进入空闲状态。

    Method for prefetching non-contiguous data structures
    10.
    发明授权
    Method for prefetching non-contiguous data structures 失效
    预取非连续数据结构的方法

    公开(公告)号：US07529895B2

    公开(公告)日：2009-05-05

    申请号：US11617276

    申请日：2006-12-28

    申请人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

    发明人： Matthias A. Blumrich ,  Dong Chen ,  Paul W. Coteus ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard D. Steinmacher-Burow ,  Todd E. Takken ,  Pavlos M. Vranas

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0862 ,  G06F9/52 ,  G06F2212/6028

    摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple perfecting for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefect rather than some other predictive algorithm. This enables hardware to effectively prefect memory access patterns that are non-contiguous, but repetitive.

    摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单完善。 存储器线被重新定义，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定哪个存储器行被提供而不是一些其它预测 算法。 这使得硬件能够有效地预处理不连续但重复的存储器访问模式。