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    STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES
    2.
    发明申请
    STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES 有权
    用于中点终端总线的静态功率降低

    公开(公告)号：US20090006683A1

    公开(公告)日：2009-01-01

    申请号：US11768552

    申请日：2007-06-26

    申请人： Paul W. Coteus ,  Todd Takken

    发明人： Paul W. Coteus ,  Todd Takken

    IPC分类号： G06F13/16

    CPC分类号： G06F13/4072 ,  G06F13/1684 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.

    摘要翻译： 公开了一种存储器系统，其包括存储器控制器和诸如DRAM的可寻址存储器件。 本发明提供一种可编程寄存器，以在总线不活动期间控制存储器系统地址和控制总线的每一位的高与低驱动状态。 以这种方式，可以使终端电压供应电流最小化，同时允许选择的总线位被驱动到所需状态。 这最大限度地减少了终端功耗，同时不影响内存系统的性能。 该技术可以扩展到其他高速公交车上。

    Tall mezzanine connector
    3.
    发明授权
    Tall mezzanine connector 失效
    高夹层连接器

    公开(公告)号：US08485831B2

    公开(公告)日：2013-07-16

    申请号：US12986132

    申请日：2011-01-06

    申请人： Thomas M. Cipolla ,  Todd Takken ,  Paul W. Coteus

    发明人： Thomas M. Cipolla ,  Todd Takken ,  Paul W. Coteus

    IPC分类号： H01R12/00

    CPC分类号： H01R13/514 ,  H01R13/6587

    摘要： A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto in such a way that there is compliance when the two halves of the circuit cards are not in alignment. The mezzanine connector comprises a header and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

    摘要翻译： 一个高夹层连接器，其连接一对位于其上的一对电路卡的每一个的大致中间，以使得当电路卡的两半不对准时具有顺应性。 夹层连接器包括集管和插座，其包括在其每个端部具有电接触装置的晶片，用于接触各个电路板中的触点，晶片通过上基部构件和下基座构件保持就位。

    ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT
    5.
    发明申请
    ERROR CORRECTING CODE WITH CHIP KILL CAPABILITY AND POWER SAVING ENHANCEMENT 有权
    错误修正代码与芯片杀伤能力和省电增强

    公开(公告)号：US20090006899A1

    公开(公告)日：2009-01-01

    申请号：US11768559

    申请日：2007-06-26

    申请人： Alan G. Gara ,  Dong Chen ,  Paul W. Coteus ,  William T. Flynn ,  James A. Marcella ,  Todd Takken ,  Barry M. Trager ,  Shmuel Winograd

    发明人： Alan G. Gara ,  Dong Chen ,  Paul W. Coteus ,  William T. Flynn ,  James A. Marcella ,  Todd Takken ,  Barry M. Trager ,  Shmuel Winograd

    IPC分类号： G06F11/26 ,  G06F11/16

    CPC分类号： G06F11/1012

    摘要： A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

    摘要翻译： 公开了一种用于检测计算机存储器系统中的存储器芯片故障的方法和系统。 该方法包括以下步骤：从一组用户数据芯片访问用户数据，以及使用来自一组系统数据芯片的数据来测试用户数据的错误。 该测试通过从用户数据生成检查符号序列来完成，将用户数据分组成数据符号序列，并计算指定的综合征序列。 如果所有的综合征为零，则用户数据没有错误。 如果其中一个校正子不为零，则计算一组鉴别符表达式，并用于确定是否发生单个或双重符号错误。 在优选实施例中，使用少于两个全系统数据芯片来测试和校正用户数据。

    Methods and apparatus using commutative error detection values for fault isolation in multiple node computers
    6.
    发明申请
    Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
    使用多节点计算机故障隔离交换误差检测值的方法和装置

    公开(公告)号：US20060248370A1

    公开(公告)日：2006-11-02

    申请号：US11106069

    申请日：2005-04-14

    申请人： Gheorghe Almasi ,  Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Sarabjeet Singh ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    发明人： Gheorghe Almasi ,  Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Sarabjeet Singh ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1633

    摘要： The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created; the node fault detection apparatus retrieves them and stores them in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in commutative error detection values indicate that the node may be faulty.

    摘要翻译： 本发明涉及在多节点计算系统中使用交换性错误检测值（例如校验和）识别和隔离故障节点来执行故障隔离的方法和装置。 在本发明中，形成多节点计算系统的节点被联网在一起，并且在程序执行期间通过网络传送信息彼此通信。 当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值并将其存储在与节点相关联的交换错误检测装置中。 间歇地，与多节点计算机系统相关联的节点故障检测装置检索保存在与节点相关联的交换性错误检测装置中的交换性错误检测值，并将其存储在存储器中。 当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值; 节点故障检测装置检索它们并将其存储在存储器中。 节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。 交换性错误检测值的差异表明节点可能有故障。

    TALL MEZZANINE CONNECTOR
    7.
    发明申请
    TALL MEZZANINE CONNECTOR 失效
    甲醇连接器

    公开(公告)号：US20120295453A1

    公开(公告)日：2012-11-22

    申请号：US13108955

    申请日：2011-05-16

    申请人： Thomas M. Cipolla ,  Paul W. Coteus ,  Todd Takken

    发明人： Thomas M. Cipolla ,  Paul W. Coteus ,  Todd Takken

    IPC分类号： H01R12/79 ,  H05K1/09

    CPC分类号： H05K1/144 ,  H01R12/716 ,  H01R12/73 ,  H01R12/79 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/10189

    摘要： A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto. The mezzanine connector comprises a and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

    摘要翻译： 一个高夹层连接器，连接一对位于其上的一对电路卡的每个的大致中间的一半。 夹层连接器包括一个和一个插座，其包括在其每个端部具有电接触装置的晶片，用于接触各个电路卡中的触点，晶片通过上部基座构件和下部基座构件保持就位。

    LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION
    10.
    发明申请
    LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
    低延迟存储器访问和同步

    公开(公告)号：US20070204112A1

    公开(公告)日：2007-08-30

    申请号：US11617276

    申请日：2006-12-28

    申请人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    发明人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    IPC分类号： G06F12/14

    CPC分类号： G06F12/0862 ,  G06F9/52 ,  G06F2212/6028

    摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

    摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单预取。 重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测 算法。 这使得硬件能够有效地预取不连续但重复的存储器访问模式。