公开(公告)号：US4926323A

公开(公告)日：1990-05-15

申请号：US163917

申请日：1988-03-03

申请人： Gigy Baror ,  Brian W. Case ,  Rod G. Fleck ,  Philip M. Freidin ,  Smeeta Gupta ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole H. Moller ,  Timothy A. Olson ,  David I. Sorensen

发明人： Gigy Baror ,  Brian W. Case ,  Rod G. Fleck ,  Philip M. Freidin ,  Smeeta Gupta ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole H. Moller ,  Timothy A. Olson ,  David I. Sorensen

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3867

摘要： A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory. The instruction fetch unit includes an instruction prefetch buffer coupled to the instruction interface for buffering a sequence of instructions supplied to the instruction interface. A branch target cache is coupled with the prefetch buffer for storing sets of instructions retrieved from a corresponding set of locations in the instruction memory, having sequential instruction addresses. The first instruction in each such set is a branch target instruction in the program.In addition, an execution unit including a data interface adapted for connection to the data memory, executes the instructions in pipeline cycles. The execution unit includes a storage facility, coupled to the data interface, for storing data in a file of data locations identified by file addresses. The storage facility includes at least two read ports and one write port operable in response to file addresses. An addressing unit coupled to receive the instructions from the instruction register, supplies the file addresses to the read ports and the write port under program control. In addition, the addressing unit is operable in response to a stack pointer providing dynamic allocation of the file of data locations to processes within the program.A memory management unit is coupled to the data interface. The memory management unit includes an address interface adapted for connection to the data memory and the instruction memory for supplying instruction addresses to the instruction memory and data addresses to the data memory, in a simple single access mode, a pipeline mode and a burst mode.

摘要翻译： 精简指令处理器响应于由流水线循环中的预先指定组成的程序来处理数据。 处理器包括指令提取单元，其包括适于连接到指令存储器并用于从指令存储器取出指令的指令接口。 指令提取单元包括指令预取缓冲器，其耦合到指令接口，用于缓冲提供给指令接口的指令序列。 分支目标高速缓冲存储器与预取缓冲器耦合，用于存储从指令存储器中的对应的一组位置检索的具有顺序指令地址的指令集。 每个这样的集合中的第一条指令是程序中的分支目标指令。 此外，包括适于连接到数据存储器的数据接口的执行单元在流水线循环中执行指令。 执行单元包括耦合到数据接口的存储设备，用于将数据存储在由文件地址标识的数据位置的文件中。 存储设备包括至少两个读端口和一个可响应文件地址操作的写端口。 耦合以从指令寄存器接收指令的寻址单元，在程序控制下将文件地址提供给读端口和写端口。 此外，寻址单元响应于堆栈指针提供动态分配数据位置文件到程序内的进程而可操作。 存储器管理单元耦合到数据接口。 存储器管理单元包括适于连接到数据存储器的地址接口和用于以简单的单次访问模式，流水线模式和突发模式向指令存储器提供指令地址和数据存储器的指令存储器。

公开(公告)号：US4777588A

公开(公告)日：1988-10-11

申请号：US771311

申请日：1985-08-30

申请人： Brian W. Case ,  Rod G. Fleck ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole Moller

发明人： Brian W. Case ,  Rod G. Fleck ,  William M. Johnson ,  Cheng-Gang Kong ,  Ole Moller

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/40 ,  G06F9/46 ,  G06F9/48 ,  G06F12/14

CPC分类号： G06F9/468 ,  G06F12/1458 ,  G06F9/4425 ,  G06F9/462

摘要： A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providing overlapping registers which are accessible to both procedures. Each procedure also has a set of "local" registers assigned to it which are inaccessible from other procedures. The register file is divided into a number of blocks and a protection register stores a word which proscribes access by a particular procedure or task to certain blocks. In this manner, an instruction processor using the register file can operate on multiple tasks maintaining the integrity of each from undesired changes occuring in the others.

摘要翻译： 公开了一种适用于精简指令集计算机（RISC）的指令处理器所使用的高速寄存器文件，其优选地以有效的寄存器分配方法使用。 寄存器文件通过动态地提供两个过程可访问的重叠寄存器来促进过程之间的参数传递。 每个过程也有一组分配给它的“本地”寄存器，不能从其他过程访问。 寄存器文件被分成多个块，并且保护寄存器存储一个单词，其禁止特定过程或任务访问某些块。 以这种方式，使用寄存器文件的指令处理器可以对多个任务进行操作，从而保持每个任务的完整性，而不是在其他任务中发生不希望的变化。

公开(公告)号：US4777587A

公开(公告)日：1988-10-11

申请号：US771327

申请日：1985-08-30

申请人： Brian W. Case ,  Rod G. Fleck ,  Cheng-Gang Kong ,  Ole Moller

发明人： Brian W. Case ,  Rod G. Fleck ,  Cheng-Gang Kong ,  Ole Moller

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/48 ,  G06F9/00 ,  G06F9/42

CPC分类号： G06F9/30058 ,  G06F9/3842

摘要： An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register. The condition bit and the branch target address determine which instruction is to be fetched, the branch not taking effect until the next-following instruction is executed. In this manner, no replacement of the instruction which physically follows the branch instruction in the pipeline need be made, and the branch occurs within the single cycle of the pipeline allocated to it. A simple circuit implements this delayed-branch method. A computer incorporating the processor readily executes special-handling techniques for calls on subroutine, interrupts and traps.

摘要翻译： 适用于简化指令集计算机的指令处理器采用在单个处理器周期中执行条件分支的指令流水线。 处理器将分支条件视为常规指令操作数，而不是单独条件代码寄存器中的特殊情况。 条件位和分支目标地址确定要获取哪个指令，分支在执行下一条指令之前不起作用。 以这种方式，不需要在流水线中物理地跟随分支指令的指令的替换，并且分支发生在分配给它的流水线的单个周期内。 一个简单的电路实现这种延迟分支方法。 结合处理器的计算机容易地执行用于子程序，中断和陷阱的调用的特殊处理技术。