利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.021 秒)

    Array access
    1.
    发明授权
    Array access 有权
    阵列访问

    公开(公告)号：US07577801B1

    公开(公告)日：2009-08-18

    申请号：US11296191

    申请日：2005-12-06

    申请人： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    发明人： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0223 ,  G06F9/30043 ,  G06F9/345

    摘要： Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.

    摘要翻译： 访问阵列中的存储器包括执行第一指令，包括通过确定第一指令使用的索引是否在有效范围内，以及在索引在有效范围内的情况下，确定与阵列元素有关的存储器地址， 对应于索引。 如果索引在有效范围内，执行第二指令来访问数组元素，访问存储器还包括至少部分地基于由第一指令确定的存储器地址的访问。

    Processor instruction used to perform a matrix test to generate a memory-related trap
    6.
    发明授权
    Processor instruction used to perform a matrix test to generate a memory-related trap 有权
    处理器指令用于执行矩阵测试以生成与存储器相关的陷阱

    公开(公告)号：US08108628B2

    公开(公告)日：2012-01-31

    申请号：US12658669

    申请日：2010-02-12

    申请人： Jack H. Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack H. Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0253 ,  G06F9/3004 ,  G06F9/3861 ,  G06F11/2236

    摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

    摘要翻译： 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

    Speculative multiaddress atomicity
    7.
    发明授权
    Speculative multiaddress atomicity 有权
    投机多地址原子性

    公开(公告)号：US07376800B1

    公开(公告)日：2008-05-20

    申请号：US11117657

    申请日：2005-04-27

    申请人： Jack H. Choquette ,  Gil Tene ,  Kevin Normoyle

    发明人： Jack H. Choquette ,  Gil Tene ,  Kevin Normoyle

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0815 ,  G06F9/528 ,  G06F2212/507

    摘要： A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

    摘要翻译： 公开了一种用于在具有多个地址的共享存储器系统中执行多个操作的技术。 该技术包括进入投机模式，对在共享存储器系统中的地址进行推测性地执行多个操作中的每一个，标记共享存储器系统中被推测为处于推测状态的地址，并且退出投机模式 其中，退出所述推测模式包括将共享存储器系统中已被操作的地址标记为处于非投机状态。

    Processor with multiple execution units and local and global register bypasses
    8.
    发明授权
    Processor with multiple execution units and local and global register bypasses 有权
    具有多个执行单元和本地和全局寄存器旁路的处理器

    公开(公告)号：US6088784A

    公开(公告)日：2000-07-11

    申请号：US281620

    申请日：1999-03-30

    申请人： Jack H. Choquette

    发明人： Jack H. Choquette

    IPC分类号： G06F9/302 ,  G06F9/38 ,  G06F15/16

    CPC分类号： G06F9/3828 ,  G06F9/3001 ,  G06F9/3826 ,  G06F9/3869 ,  G06F9/3885

    摘要： A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.

    摘要翻译： 公开了一种使用局部和全局寄存器旁路在多个执行单元之间进行数据处理的方法和装置。 在一个实施例中，该装置包含寄存器文件，至少两个旁路电路，多个执行单元和控制电路。 每个旁路电路连接至少一个执行单元。 耦合到执行单元的控制电路限制每个执行时钟周期不超过一个时钟延迟。 控制电路还指定用于处理延迟的延迟时钟周期。

    Method and apparatus for vector register with scalar values
    9.
    发明授权
    Method and apparatus for vector register with scalar values 有权
    具有标量值的向量寄存器的方法和装置

    公开(公告)号：US06530011B1

    公开(公告)日：2003-03-04

    申请号：US09422045

    申请日：1999-10-20

    申请人： Jack H. Choquette

    发明人： Jack H. Choquette

    IPC分类号： G06F1582

    CPC分类号： G06F9/30036 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30109 ,  G06F2207/382 ,  G06F2207/3828

    摘要： A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar register and a second data in a vector register. Upon fetching the first data as a first operand and the second data as a second operand, the processing unit performs an operation between the first and second operands in response to an operator. After operations, the result is subsequently stored in a second scalar register.

    摘要翻译： 一种用于在数字处理系统中实现混合标量和向量值的方法和装置。 在一个实施例中，包含处理单元和存储器的数字处理系统能够识别第一标量寄存器中的第一数据和矢量寄存器中的第二数据。 在将第一数据作为第一操作数获取并且第二数据作为第二操作数获取时，处理单元响应于操作者在第一和第二操作数之间执行操作。 在操作之后，结果随后存储在第二标量寄存器中。

    Floating-point and integer multiply-add and multiply-accumulate
    10.
    发明授权
    Floating-point and integer multiply-add and multiply-accumulate 失效
    浮点和整数乘法和乘法累加

    公开(公告)号：US06480872B1

    公开(公告)日：2002-11-12

    申请号：US09235148

    申请日：1999-01-21

    申请人： Jack H. Choquette

    发明人： Jack H. Choquette

    IPC分类号： G06F700

    CPC分类号： G06F7/5443 ,  G06F2207/3824

    摘要： A method and a device including, in one embodiment, a multiply array and at least one adder to perform a floating-point multiplication followed by an addition when operands are in floating-point format. The device is also configured to perform an integer multiplication followed by an accumulation when operands are in integer format. The device is further configured to perform a floating-point multiply-add or an integer multiply-accumulation in response to control signals. In another embodiment, the device contains an adder and the adder is capable of performing a floating-point addition and an integer accumulation. The adder is configured to be extra wide to reduce operand misalignment. Moreover, the device stalls the process in response to operand misalignment.

    摘要翻译： 一种方法和装置，在一个实施例中，包括乘法阵列和至少一个加法器，以在操作数处于浮点格式时执行浮点乘法，随后加法。 该设备还被配置为当整数格式的操作数时，执行整数乘法后跟累加。 该设备还被配置为响应于控制信号执行浮点乘法加法或整数乘法累积。 在另一实施例中，该装置包含加法器，并且加法器能够执行浮点加法和整数累加。 加法器被配置为超宽以减少操作数失准。 此外，设备响应于操作数未对准而使进程停止。