利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

56 条记录 (耗时 0.021 秒)

    Speculative multiaddress atomicity
    1.
    发明授权
    Speculative multiaddress atomicity 有权
    投机多地址原子性

    公开(公告)号：US07376800B1

    公开(公告)日：2008-05-20

    申请号：US11117657

    申请日：2005-04-27

    申请人： Jack H. Choquette ,  Gil Tene ,  Kevin Normoyle

    发明人： Jack H. Choquette ,  Gil Tene ,  Kevin Normoyle

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0815 ,  G06F9/528 ,  G06F2212/507

    摘要： A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.

    摘要翻译： 公开了一种用于在具有多个地址的共享存储器系统中执行多个操作的技术。 该技术包括进入投机模式，对在共享存储器系统中的地址进行推测性地执行多个操作中的每一个，标记共享存储器系统中被推测为处于推测状态的地址，并且退出投机模式 其中，退出所述推测模式包括将共享存储器系统中已被操作的地址标记为处于非投机状态。

    Processor instruction used to perform a matrix test to generate a memory-related trap
    2.
    发明授权
    Processor instruction used to perform a matrix test to generate a memory-related trap 有权
    处理器指令用于执行矩阵测试以生成与存储器相关的陷阱

    公开(公告)号：US08108628B2

    公开(公告)日：2012-01-31

    申请号：US12658669

    申请日：2010-02-12

    申请人： Jack H. Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack H. Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0253 ,  G06F9/3004 ,  G06F9/3861 ,  G06F11/2236

    摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

    摘要翻译： 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

    Array access
    4.
    发明授权
    Array access 有权
    阵列访问

    公开(公告)号：US07577801B1

    公开(公告)日：2009-08-18

    申请号：US11296191

    申请日：2005-12-06

    申请人： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    发明人： Gil Tene ,  Jack H. Choquette ,  Scott Sellers ,  Cliff N. Click, Jr.

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0223 ,  G06F9/30043 ,  G06F9/345

    摘要： Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.

    摘要翻译： 访问阵列中的存储器包括执行第一指令，包括通过确定第一指令使用的索引是否在有效范围内，以及在索引在有效范围内的情况下，确定与阵列元素有关的存储器地址， 对应于索引。 如果索引在有效范围内，执行第二指令来访问数组元素，访问存储器还包括至少部分地基于由第一指令确定的存储器地址的访问。

    ACCELERATED CLASS CHECK
    6.
    发明申请
    ACCELERATED CLASS CHECK 有权
    加速类检查

    公开(公告)号：US20110321064A1

    公开(公告)日：2011-12-29

    申请号：US13227111

    申请日：2011-09-07

    申请人： Gil Tene ,  Cliff N. Click, JR. ,  Murali Sundaresan ,  Michael A. Wolf

    发明人： Gil Tene ,  Cliff N. Click, JR. ,  Murali Sundaresan ,  Michael A. Wolf

    IPC分类号： G06F9/42

    CPC分类号： G06F9/4428 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/4488 ,  G06F9/449 ,  G06F9/455

    摘要： Handling a virtual method call includes extracting, from a pointer to an object, an identifier associated with the class of the object, the pointer to the object being associated with the virtual method call, and the identifier being embedded within the pointer; using the identifier to obtain a virtual method table, including locating a first entry in a class identifier table mapping a plurality of class identifiers to a corresponding plurality of class data, the first entry being associated with the identifier and comprising the virtual method table or a pointer used to obtain the virtual method table; locating a second entry in the virtual method table, the second entry being associated with the virtual method call; and jumping to an address associated with the second entry to execute code at the address.

    摘要翻译： 处理虚拟方法调用包括从对象的指针提取与对象的类相关联的标识符，与虚拟方法调用相关联的对象的指针，以及嵌入在指针内的标识符; 使用所述标识符来获得虚拟方法表，包括将映射多个类标识符的类标识符表中的第一条目定位到对应的多个类数据，所述第一条目与所述标识符相关联，并且包括所述虚方法表或 指针用于获取虚拟方法表; 在虚拟方法表中定位第二条目，第二条目与虚拟方法调用相关联; 并跳转到与第二条目相关联的地址，以在该地址处执行代码。

    Processor instruction used to determine whether to perform a memory-related trap
    8.
    发明申请
    Processor instruction used to determine whether to perform a memory-related trap 有权
    处理器指令用于确定是否执行内存相关的陷阱

    公开(公告)号：US20100153689A1

    公开(公告)日：2010-06-17

    申请号：US12658669

    申请日：2010-02-12

    申请人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    发明人： Jack Choquette ,  Gil Tene ,  Michael A. Wolf

    IPC分类号： G06F9/38 ,  G06F12/10

    CPC分类号： G06F12/0253 ,  G06F9/3004 ,  G06F9/3861 ,  G06F11/2236

    摘要： Instruction execution includes fetching an instruction that comprises a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value. It further includes executing the instruction to determine whether to perform a trap, wherein executing the instruction includes selecting from a plurality of tests at least one test for determining whether to perform a trap and carrying out the at least one test. The second set of one or more bits is used in the determination of whether to perform the trap; and the plurality of tests includes a matrix test that determines whether a data value being stored as pointed to by the first address value is escaping from one of a plurality of managed memory types to another one of the plurality of managed memory types and generates a trap in the event that the data value is determined to be escaping from one of the plurality of managed memory types to another one of the plurality of managed memory types, wherein the matrix test is based on a matrix associated with garbage collection and a matrix entry located using at least some of the first set of one or more bits and at least some of the second set of one or more bits.

    摘要翻译： 指令执行包括获取包括识别指令的一个或多个比特的第一组的指令，以及与第一地址值相关联的一个或多个比特的第二组。 它还包括执行指令以确定是否执行陷阱，其中执行指令包括从多个测试中选择至少一个用于确定是否执行陷阱并进行至少一个测试的测试。 在确定是否执行陷阱时使用第二组一个或多个比特; 并且所述多个测试包括矩阵测试，所述矩阵测试确定由所述第一地址值指示的存储的数据值是否从多个管理存储器类型中的一个转移到所述多个管理存储器类型中的另一个，并产生陷阱 在数据值被确定为从多个托管存储器类型之一转移到多个托管存储器类型中的另一个的情况下，其中矩阵测试基于与垃圾收集相关联的矩阵和位于 使用一个或多个比特的第一组中的至少一些以及一个或多个比特的第二组中的至少一些。

    Segmented virtual machine transport mechanism
    9.
    发明申请
    Segmented virtual machine transport mechanism 有权
    分段虚拟机传输机制

    公开(公告)号：US20090178039A1

    公开(公告)日：2009-07-09

    申请号：US12315854

    申请日：2008-12-05

    申请人： Gil Tene ,  Michael A. Wolf ,  Anirban Sengupta ,  Sivakumar Annamalai ,  Adrian Sun

    发明人： Gil Tene ,  Michael A. Wolf ,  Anirban Sengupta ,  Sivakumar Annamalai ,  Adrian Sun

    IPC分类号： G06F9/455

    CPC分类号： G06F9/544 ,  G06F9/45533

    摘要： Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.

    摘要翻译： 公开了向分段虚拟机（VM）上运行的应用提供数据。 提供数据包括打开分段的VM和外部数据源之间的接口，将数据从外部数据源传送到接口缓冲器，将第一选定数量的数据从接口缓冲器传送到壳VM缓冲器，传送第二选定量 的数据从shell VM缓冲区提供到核心VM缓冲区，以及响应于来自应用程序的读取请求，将数据从核心VM缓冲区提供给应用程序。