公开(公告)号：US07642629B2

公开(公告)日：2010-01-05

申请号：US11891867

申请日：2007-08-13

申请人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

发明人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

摘要翻译： 一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层， 至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

公开(公告)号：US20050205977A1

公开(公告)日：2005-09-22

申请号：US11125624

申请日：2005-05-10

申请人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

发明人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC分类号： G01R20060101 ,  H01L21/44 ,  H01L23/02 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

摘要翻译： 一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层， 至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

公开(公告)号：US20080012115A1

公开(公告)日：2008-01-17

申请号：US11891867

申请日：2007-08-13

申请人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

发明人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC分类号： H01L23/48

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

摘要翻译： 一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层， 至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

公开(公告)号：US07265440B2

公开(公告)日：2007-09-04

申请号：US11125624

申请日：2005-05-10

申请人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

发明人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC分类号： H01L23/02 ,  H01L21/44

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

摘要翻译： 一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层， 至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

公开(公告)号：US06972480B2

公开(公告)日：2005-12-06

申请号：US10462576

申请日：2003-06-16

申请人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

发明人： Gil Zilber ,  Reuven Katraro ,  Julia Aksenton ,  Vage Oganesian

IPC分类号： G01R20060101 ,  H01L21/44 ,  H01L23/02 ,  H01L23/31 ,  H01L23/485 ,  H01L23/495

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

公开(公告)号：US07033664B2

公开(公告)日：2006-04-25

申请号：US10277498

申请日：2002-10-22

申请人： Gil Zilber ,  Reuven Katraro ,  Doron Teomim

发明人： Gil Zilber ,  Reuven Katraro ,  Doron Teomim

IPC分类号： B32B3/24 ,  B32B3/10 ,  H01L23/02

CPC分类号： H01L24/02 ,  H01L23/3114 ,  H01L2224/0401 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10T428/23 ,  Y10T428/231 ,  Y10T428/239 ,  Y10T428/24273 ,  Y10T428/24322 ,  Y10T428/24562 ,  Y10T428/24661 ,  Y10T428/24744

摘要： A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.

摘要翻译： 一种基于晶体衬底的器件，包括在其上形成有微观结构的晶体衬底和至少一个封装层，所述至少一个封装层形成在所述微结构之上，并且与所述至少一个封装层形成在所述结构衬底和所述至少一个封装层之间的至少一个间隙， 所述包装层与所述至少一个间隙连通。

公开(公告)号：US20120300363A1

公开(公告)日：2012-11-29

申请号：US13567317

申请日：2012-08-06

申请人： Reuven Katraro ,  Nissim Cohen ,  Marina Kravchik-Volfson ,  Eli Bershadsky ,  John Bultitude

发明人： Reuven Katraro ,  Nissim Cohen ,  Marina Kravchik-Volfson ,  Eli Bershadsky ,  John Bultitude

IPC分类号： H01G4/12

CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01G9/052 ,  H01G9/055 ,  Y10T29/435

摘要： A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

摘要翻译： 大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。 例如通过氧化在多孔陶瓷体上形成电介质层。 导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。 然后电容器可以用各种层封装，并且可以包括常规的电终端。 制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体，氧化以形成电介质层，并用导电介质填充多孔体以形成第二电极。 也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。

公开(公告)号：US07426102B2

公开(公告)日：2008-09-16

申请号：US11415039

申请日：2006-05-01

申请人： Haim Goldberger ,  Reuven Katraro ,  Doron Gozaly

发明人： Haim Goldberger ,  Reuven Katraro ,  Doron Gozaly

IPC分类号： H01G4/228

CPC分类号： H01G4/228 ,  H01G4/33 ,  H01L2224/11

摘要： An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted. The standoff provides resistance to tilting.

摘要翻译： 诸如电容器的电子部件包括具有第一和第二主表面的基板，覆盖基板的第一主表面的电介质层，第一电极和第二电极。 存在覆盖第一和第二电极的钝化层，第一开口形成在第一电极上的钝化层中，第二开口形成在第二电极上的钝化层中。 第一底部电极终端位于第一开口中，而第二底部电极终端位于第二开口中。 第一底部电极端子电连接到第一电极，第二底部电极端子电连接到第二电极。 间隔件位于第一底部电极端子和第二底部电极端子之间并且附接到钝化层，从而在安装时为电子部件提供支撑。 对立提供了对倾斜的抵抗力。

公开(公告)号：US08238076B2

公开(公告)日：2012-08-07

申请号：US12553508

申请日：2009-09-03

申请人： Reuven Katraro ,  Nissim Cohen ,  Marina Kravchik-Volfson ,  Eli Bershadsky ,  John Bultitude

发明人： Reuven Katraro ,  Nissim Cohen ,  Marina Kravchik-Volfson ,  Eli Bershadsky ,  John Bultitude

IPC分类号： H01G4/00

CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01G9/052 ,  H01G9/055 ,  Y10T29/435

摘要： A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

摘要翻译： 大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。 例如通过氧化在多孔陶瓷体上形成电介质层。 导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。 然后电容器可以用各种层封装，并且可以包括常规的电终端。 制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体，氧化以形成电介质层，并用导电介质填充多孔体以形成第二电极。 也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。

公开(公告)号：US20100073846A1

公开(公告)日：2010-03-25

申请号：US12553508

申请日：2009-09-03

申请人： Reuven Katraro ,  Nissim Cohen ,  Marina Kravchik-Volfson ,  Eli Bershadsky ,  John Bultitude

发明人： Reuven Katraro ,  Nissim Cohen ,  Marina Kravchik-Volfson ,  Eli Bershadsky ,  John Bultitude

IPC分类号： H01G4/06 ,  H01G7/00

CPC分类号： H01G9/15 ,  H01G9/0032 ,  H01G9/052 ,  H01G9/055 ,  Y10T29/435

摘要： A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

摘要翻译： 大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。 例如通过氧化在多孔陶瓷体上形成电介质层。 导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。 然后电容器可以用各种层封装，并且可以包括常规的电终端。 制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体，氧化以形成电介质层，并用导电介质填充多孔体以形成第二电极。 也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。