公开(公告)号：US12080600B2

公开(公告)日：2024-09-03

申请号：US17010610

申请日：2020-09-02

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/78 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4857 ,  H01L21/561 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05011 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05083 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/0535 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/186 ,  H01L2924/351 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/92 ,  H01L21/78 ,  H01L2224/19 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11

Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

公开(公告)号：US12062622B2

公开(公告)日：2024-08-13

申请号：US17883568

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Ping Pu ,  Hsiao-Wen Lee

IPC: H01L23/538 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

公开(公告)号：US11955460B2

公开(公告)日：2024-04-09

申请号：US17063251

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Da Tsai ,  Meng-Tse Chen ,  Sheng-Feng Weng ,  Sheng-Hsiang Chiu ,  Wei-Hung Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2224/0237 ,  H01L2224/024 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/06 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0715 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19102 ,  H01L2924/3511

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

公开(公告)号：US11908816B2

公开(公告)日：2024-02-20

申请号：US17538133

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0239 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05193 ,  H01L2224/13026 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0509 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/05994

Abstract: The present application discloses a method for fabricating a semiconductor device with graphene layers The method includes providing a substrate; forming a first passivation layer above the substrate; forming a redistribution layer on the first passivation layer; forming a first adjustment layer on the redistribution layer; forming a pad layer on the first adjustment layer; forming a second adjustment layer between the pad layer and the first adjustment layer; forming a second passivation layer on the first passivation layer; wherein the first adjustment layer and the second adjustment layer are formed of graphene.

公开(公告)号：US11901318B2

公开(公告)日：2024-02-13

申请号：US17160400

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Aaron Chen ,  Chi Ren ,  Yi Hsin Liu

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L23/53228 ,  H01L23/53257 ,  H01L2224/024 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0391 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

公开(公告)号：US20240021548A1

公开(公告)日：2024-01-18

申请号：US17863491

申请日：2022-07-13

Applicant: Taiwan Semiconductor Manufacturing Company

Inventor： Wei-Chun Liao ,  Guo-Zhou Huang ,  Huan-Kuan Su ,  Yu-Hong Pan ,  Wen Han Hung ,  Ling-Sung Wang

IPC: H01L23/00

CPC classification number: H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/13024 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/05042 ,  H01L2924/0535 ,  H01L2924/07025 ,  H01L2924/35121

Abstract: A semiconductor device and method of manufacturing that includes a first etch stop layer and a second etch stop layer to prevent delamination and damage to underlying components. A first passivation layer and a second passivation layer are disposed on a substrate, with a metal pad exposed through the passivation layers and contacting a top metal component of the substrate. The first etch stop layer is then formed on the second passivation layer and the metal pad. A third passivation layer is then formed on the substrate with an opening to the metal pad, which is covered by the first etch stop layer. The second etch stop layer is then formed on the third passivation layer and in the opening on the second etch stop layer. A bottom metal film/conductive component is then formed on the second etch stop layer, photoresist is applied, and wet etching is performed. The metal pad is protected from damage caused by delamination of the second etch stop layer by the first etch stop layer.

公开(公告)号：US11854784B2

公开(公告)日：2023-12-26

申请号：US17989498

申请日：2022-11-17

Applicant: MediaTek Inc.

Inventor： Yen-Yao Chi ,  Nai-Wei Liu ,  Ta-Jen Yu ,  Tzu-Hung Lin ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/13024

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US20230268275A1

公开(公告)日：2023-08-24

申请号：US17651883

申请日：2022-02-21

Applicant: International Business Machines Corporation

Inventor： Mukta Ghate Farooq ,  James J. Kelly ,  Eric Perfecto ,  SPYRIDON SKORDAS ,  Dale Curtis McHerron

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L23/5329 ,  H01L24/05 ,  H01L21/02118 ,  H01L2924/01029 ,  H01L2224/024

Abstract: A semiconductor element includes a conductive pad. The semiconductor element further includes a first layer of a first polyimide material having an uppermost surface. The first layer includes a via trench extending through the first layer from the uppermost surface to the conductive pad. The semiconductor element further includes a second layer of a second polyimide material arranged in direct contact with the uppermost surface. The second layer includes a line trench extending to the uppermost surface. The semiconductor element further includes a conductive structure arranged in the via trench and the line trench such that copper is in direct contact with the second polyimide material.

公开(公告)号：US20230260939A1

公开(公告)日：2023-08-17

申请号：US18308883

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chen ,  Ching-Tien Su

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L24/81 ,  H01L21/563 ,  H01L21/78 ,  H01L25/105 ,  H01L23/3142 ,  H01L24/96 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L24/32 ,  H01L24/83 ,  H01L24/03 ,  H01L2924/3512 ,  H01L2224/0391 ,  H01L2224/0231 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/02371 ,  H01L2224/13024 ,  H01L2225/1058 ,  H01L2225/1023 ,  H01L2224/831 ,  H01L2224/32145 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/11334 ,  H01L24/11 ,  H01L2224/11849 ,  H01L2224/1146 ,  H01L2224/03002 ,  H01L21/568 ,  H01L21/76816

Abstract: A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

公开(公告)号：US20190206820A1

公开(公告)日：2019-07-04

申请号：US15856236

申请日：2017-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rafael Jose Lizares GUEVARA, III

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/024 ,  H01L2224/11001 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/1403 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/3841

Abstract: A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.