公开(公告)号：US20070019492A1

公开(公告)日：2007-01-25

申请号：US11401523

申请日：2006-04-11

申请人： Giovanni Campardo ,  Gian Vanalli ,  Pier Stoppino ,  Roberto Dossi ,  Aldo Losavio

发明人： Giovanni Campardo ,  Gian Vanalli ,  Pier Stoppino ,  Roberto Dossi ,  Aldo Losavio

IPC分类号： G11C5/14

CPC分类号： G11C16/30

摘要： A low supply voltage memory device includes a first supply pin and a second supply pin for the connection to a first supply voltage source (VDD) and to a second supply voltage source (VDDQ). The device may include a memory and at least one booster overlapped by way of a “system in package” system and in particular with “stacked-die” technology. This booster may be connected to the memory by way of a plurality of discrete components.

摘要翻译： 低电源电压存储器件包括用于连接到第一电源电压源（VDD）和第二电源电压源（VDDQ）的第一电源引脚和第二电源引脚。 该装置可以包括存储器和至少一个通过“系统在封装”系统中重叠的增压器，特别是具有“堆叠式芯片”技术。 该升压器可以通过多个分立组件连接到存储器。

公开(公告)号：US07616515B2

公开(公告)日：2009-11-10

申请号：US11401523

申请日：2006-04-11

申请人： Giovanni Campardo ,  Gian Pietro Vanalli ,  Pier Paolo Stoppino ,  Roberto Dossi ,  Aldo Losavio

发明人： Giovanni Campardo ,  Gian Pietro Vanalli ,  Pier Paolo Stoppino ,  Roberto Dossi ,  Aldo Losavio

IPC分类号： G11C5/14

CPC分类号： G11C16/30

摘要： An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the at least one booster and associated therewith in a “system in a package configuration.”

摘要翻译： 集成电子设备包括至少一个电源引脚和耦合到所述至少一个电源引脚的至少一个升压器。 而且，至少有一个集成电路由至少一个升压器供电并与“封装配置中的系统”相关联。

公开(公告)号：US20070023871A1

公开(公告)日：2007-02-01

申请号：US11192981

申请日：2005-07-29

申请人： Roberto Dossi

发明人： Roberto Dossi

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of the first side or the second side of the semiconductor device along a second direction. The chip level contact portions extend along the first direction. Ends of the chip level contact portions are aligned along a line extending along the second direction. This leadframe can be included with a semiconductor chip in a packaged integrated circuit.

摘要翻译： 引线框架包括多个引线。 引线具有板级接触部分，中间部分和芯片级接触部分。 中间部分设置在板级接触部分和芯片级接触部分之间。 板级接触部分沿着第二方向从半导体器件的第一侧或第二侧中的一个延伸。 芯片级接触部分沿着第一方向延伸。 芯片级接触部分的端部沿着沿第二方向延伸的线排列。 该引线框可以包含在封装集成电路中的半导体芯片中。

公开(公告)号：US20080150111A1

公开(公告)日：2008-06-26

申请号：US11644044

申请日：2006-12-22

申请人： Dietmar Hiller ,  Roberto Dossi ,  Andreas Knoblauch

发明人： Dietmar Hiller ,  Roberto Dossi ,  Andreas Knoblauch

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other, each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit, wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.

摘要翻译： 一种存储器件，包括相对于彼此交错排列的堆叠存储器管芯的至少一个存储器堆叠，所述存储器堆叠的每个堆叠存储器管芯沿着其边缘管芯焊盘包括用于将所述堆叠的存储管芯接合到所述存储器件的可连接的衬底焊盘 控制电路，其中将所述存储器管芯单独地连接到所述控制电路的堆叠存储器管芯的每个管芯焊盘与所述堆叠式存储器管芯的管芯焊盘相比具有增加的距离（d i i i i） 将所述堆叠的存储器管芯与所述存储器堆叠的其它堆叠的存储器管芯的相应管芯焊盘并联连接到所述控制电路。

公开(公告)号：US07875985B2

公开(公告)日：2011-01-25

申请号：US11644044

申请日：2006-12-22

申请人： Dietmar Hiller ,  Roberto Dossi ,  Andreas Knoblauch

发明人： Dietmar Hiller ,  Roberto Dossi ,  Andreas Knoblauch

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A memory device comprising at least one memory stack of stacked memory dies which are staggered with respect to each other, each stacked memory die of said memory stack comprising along its edge die pads for bonding said stacked memory die to substrate pads of said memory device connectable to a control circuit, wherein each die pad of a stacked memory die which connects said memory die individually to said control circuit comprises an increased distance (di) in comparison to die pads of said stacked memory die which connect said stacked memory die in parallel with corresponding die pads of other stacked memory dies of said memory stack to said control circuit.

摘要翻译： 一种存储器件，包括相对于彼此交错排列的堆叠存储器管芯的至少一个存储器堆叠，所述存储器堆叠的每个堆叠存储器管芯沿着其边缘管芯焊盘包括用于将所述堆叠的存储管芯接合到所述存储器件的可连接的衬底焊盘 控制电路，其中将所述存储器管芯单独地连接到所述控制电路的堆叠存储器管芯的每个管芯焊盘与所述堆叠式存储器管芯的管芯焊盘相比增加了距离（di），所述管芯焊盘将所述堆叠的存储器管芯与 将所述存储器堆叠的其它堆叠存储器管芯的相应管芯焊盘连接到所述控制电路。

公开(公告)号：US07348660B2

公开(公告)日：2008-03-25

申请号：US11192981

申请日：2005-07-29

申请人： Roberto Dossi

发明人： Roberto Dossi

IPC分类号： H01L23/495

CPC分类号： H01L23/4951 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00

摘要： A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The board level contact portions extend from one of the first side or the second side of the semiconductor device along a second direction. The chip level contact portions extend along the first direction. Ends of the chip level contact portions are aligned along a line extending along the second direction. This leadframe can be included with a semiconductor chip in a packaged integrated circuit.

摘要翻译： 引线框架包括多个引线。 引线具有板级接触部分，中间部分和芯片级接触部分。 中间部分设置在板级接触部分和芯片级接触部分之间。 板级接触部分沿着第二方向从半导体器件的第一侧或第二侧中的一个延伸。 芯片级接触部分沿着第一方向延伸。 芯片级接触部分的端部沿着沿第二方向延伸的线排列。 该引线框可以包含在封装集成电路中的半导体芯片中。