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公开(公告)号：US4556978A
公开(公告)日：1985-12-03
申请号：US515401
申请日：1983-07-20
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.
摘要翻译： 公开了适用于门阵列中的LSI实现的72位移位矩阵。 8字节移位器和8位移位器被组合以产生0-72个位置的方向，圆形或开放的零位或符号填充位移。 另外提供了一种装置，用于从矩阵输出再生原始源奇偶校验以用于通过检查。 单个9位奇偶校验发生器是检查矩阵正确性所需要的。
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公开(公告)号：US4595911A
公开(公告)日：1986-06-17
申请号：US514208
申请日：1983-07-14
CPC分类号： G06F9/30025 , G06F5/012 , G06F9/30036 , G06F9/30167
摘要： A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.
摘要翻译： 描述了利用可编程控制的多路复用器级别的高速系统，用于将数据从可编程选择的第一格式重新格式化为第二格式。 利用交错的输入数据优化重新格式化速率。 重新格式化系统提供了现场选择和理由，以及所选领域的补充和量产能力。 可以解包两种不同浮点格式的浮点操作数，即从尾数分离的特性和正确对齐的特征，并且可以通过将特征与相关尾数进行定位和重组来进行打包。 在整个重新格式化过程中，维持所选位分组的奇偶校验，从而允许通过检查重新格式化操作。 重新格式化系统包括可编程选择的恒定生成。
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公开(公告)号：US4366548A
公开(公告)日：1982-12-28
申请号：US221981
申请日：1981-01-02
CPC分类号： G06F7/502 , G06F7/485 , G06F7/508 , G06F9/30014 , G06F9/30036 , G06F2207/382 , G06F2207/3836 , G06F7/4991
摘要： A characteristic adder for use in a data processing system that performs floating-point arithmetic operations is described. A 1's complement subtractive adder is shown for forming the sum or difference of a pair of exponents under control of function control circuitry, along with an indication of which characteristic is larger for selecting which mantissa operand should be shifted for proper alignment. The function control circuitry responds to function signals to select addition or subtraction, provide the magnitude or complement of the results, and select between two available floating-point formats. Characteristic Overflow and Underflow is tested and signaled for each of the two possible floating-point formats.
摘要翻译： 描述用于执行浮点算术运算的数据处理系统中的特征加法器。 示出了1的补码减法加法器，用于在功能控制电路的控制下形成一对指数的和或差，以及哪个特性较大的指示，用于选择哪个尾数操作数应被移位以进行适当的对准。 功能控制电路响应功能信号选择加法或减法，提供结果的大小或互补，并在两种可用的浮点格式之间进行选择。 针对两种可能的浮点格式中的每一种测试特征溢出和下溢信号。
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4.发明授权Isolation for failures of input signals supplied to dual modules which are checked by comparison 失效通过比较检查提供给双模块的输入信号故障的隔离
公开(公告)号：US4943969A
公开(公告)日：1990-07-24
申请号：US277074
申请日：1988-11-28
申请人： Peter B. Criswell
发明人： Peter B. Criswell
IPC分类号： G06F11/16
CPC分类号： G06F11/1608
摘要： Failures of duplicate input signals to two indentical electronic modules which may be units, cards, circuits or other entity, are detected by comparison. In each electronic module functional input signals are captured in a plurality of latches on different, or the same, clock phase. Each input signal is captured directly in latches on the same phase as the functional latch which used it to provide a plurality of link signals which are encoded by techniques, such as parity or residue encoding, and compared. The result of the link signal comparison is stored in a register. The outputs of the register are encoded and are supplied to a comparator which compares a signal from the other identical electronic modules. When miscomparison occurs location of the type of failue is facilitated by the system.
摘要翻译： 通过比较可以检测到可能是单元，卡，电路或其他实体的两个独立电子模块的重复输入信号的故障。 在每个电子模块中，功能输入信号被捕获在不同的或相同的时钟相位上的多个锁存器中。 每个输入信号被直接捕获在与功能锁存器相同的相位上的锁存器中，该功能锁存器用于提供由诸如奇偶校验或残差编码的技术编码的多个链路信号，并进行比较。 链接信号比较的结果存储在寄存器中。 寄存器的输出被编码并提供给比较器，比较器来自其他相同的电子模块的信号。 当错误比较发生时，故障类型的位置由系统方便。
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5.发明授权System for checking duplicate logic using complementary residue codes to achieve high error coverage with a minimum of interface signals 失效使用互补残留代码检查重复逻辑的系统，以最少的接口信号实现高错误覆盖
公开(公告)号：US4924467A
公开(公告)日：1990-05-08
申请号：US235425
申请日：1988-08-24
申请人： Peter B. Criswell
发明人： Peter B. Criswell
CPC分类号： G06F11/1608 , G06F11/104
摘要： A system for detecting and isolating fault conditions occurring within a digital electronic system. The digital electronic system includes a first digital logic array for generating digital outputs in response to a set of digital signal inputs applied to it. The digital logic array is replicated and the second array is configured to receive the same inputs as the first. The first and second arrays are made to operate in synchrony so as to normally produce identical outputs in the absence of fault conditions occurring either in the first or second array or in the inputs applied to them. The digital outputs from the first array are applied to first and second residue code generators having different modulii. Likewise, the outputs from the second arry are applied to third and fourth residue code generators which are identical in make-up to the first and second residue code generators. The residue codes developed by the first and third generators are applied to a first comparator while the codes developed by the second and fourth generators are applied to a second comparator. The comparator outputs are applied through combinatorial logic so as to provide an output signal indicative of a fault condition when either the first or second comparator produces an output indicative of inequality between respective residue codes.
摘要翻译： 一种用于检测和隔离数字电子系统内出现的故障状况的系统。 数字电子系统包括用于响应于应用于其的一组数字信号输入而产生数字输出的第一数字逻辑阵列。 数字逻辑阵列被复制，第二阵列被配置为接收与第一阵列相同的输入。 使第一和第二阵列同步操作，以便在没有发生在第一或第二阵列中或在施加到它们的输入中的故障条件下通常产生相同的输出。 来自第一阵列的数字输出被应用于具有不同模块的第一和第二残差码发生器。 类似地，来自第二arry的输出被应用于第三和第四残差码发生器，它们与第一和第二残留码发生器相同。 由第一和第三发生器开发的残留代码被应用于第一比较器，而由第二和第四发生器开发的代码被施加到第二比较器。 比较器输出通过组合逻辑施加，以便当第一或第二比较器产生指示各残留代码之间的不等式的输出时，提供指示故障状况的输出信号。
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6.发明授权Method and a means for checking normalizing operations in a computer device 失效方法和用于检查计算机设备中的归一化操作的装置
公开(公告)号：US4528640A
公开(公告)日：1985-07-09
申请号：US397760
申请日：1982-07-13
申请人： Peter B. Criswell
发明人： Peter B. Criswell
IPC分类号： G06F11/00
CPC分类号： G06F11/0763
摘要： A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is used in conjunction with the main normalizer of the arithmetic unit to determine if the result is indeed normalized. Where the post normalize count is zero, an error designator remains inactivated. However, where the count is non-zero, the error designator is activated to indicate an error exists, unless it is disabled by separate circuitry which detects that the number being shifted is .+-..0.. The preferred embodiment disclosed herein checks the operation of a pair of 72-bit main normalizers with a single 13-bit post normalizer. A plurality of instructions in which this check is significant are illustrated.
摘要翻译： 公开了一种用于在单精度和双精度操作中通过涉及整数和浮点格式的数据处理系统的运算单元的归一化器操作的方法和装置。 后归一化器与算术单元的主归一化器结合使用以确定结果是否确实被归一化。 在归一化计数为零的情况下，错误指示符仍然停用。 然而，在计数不为零的情况下，错误指示器被激活以指示存在错误，除非由检测到被移位的数字为+/- O的单独电路禁用。 本文中公开的优选实施例使用单个13位后归一化器来检查一对72位主规范化器的操作。 示出了该检查是重要的多个指令。
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7.发明授权Dual microcode RAM address mode instruction execution using operation code RAM storing control words with alternate address indicator 有权使用操作码RAM存储具有备用地址指示符的控制字的双微码RAM地址模式指令执行公开(公告)号：US06654875B1
公开(公告)日：2003-11-25
申请号：US09572511
申请日：2000-05-17
IPC分类号： G06F930
CPC分类号： G06F9/30189 , G06F9/30145 , G06F9/30181 , G06F9/382 , G06F9/3867
摘要： Instruction processor and method supporting dual-mode execution of computer instructions. In various embodiments, certain instructions are executable in one of two modes. The first mode is compatible with the native instruction set and data words, and the second mode is an adaptation suitable for platform independent instructions. A control word RAM is addressed by the operation code of an instruction, and each word in the control word RAM includes an address into a microcode RAM. The address into the microcode RAM is manipulated in accordance with the various embodiments to reference either a first set of microcode for native instructions and data words, or a second set of microcode for execution in a platform-independent mode.
摘要翻译： 指令处理器和方法支持双模式执行计算机指令。 在各种实施例中，某些指令可以以两种模式之一执行。 第一种模式与本机指令集和数据字兼容，第二种模式是适合平台无关指令的适配。 控制字RAM由指令的操作码寻址，并且控制字RAM中的每个字都包括到微码RAM中的地址。 根据各种实施例，对微代码RAM的地址进行操作以引用用于本地指令和数据字的第一组微代码，或者以与平台无关的模式来执行的第二组微代码。
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8.发明授权
公开(公告)号：US5077739A
公开(公告)日：1991-12-31
申请号：US353307
申请日：1989-05-17
申请人： Peter B. Criswell
发明人： Peter B. Criswell
CPC分类号： G06F11/0721 , G06F11/0751 , G06F11/1641 , G06F11/2205
摘要： An instruction processor for a data processing system runs arithmetic sequences that are initiated by sequence designator signals and are interrupted by interrupt signals. During operation of the processor logic elements of the processor are selectively cleared by clear signals during time periods that sequence designator signals are in inactive states following the occurrence of an interrupt signal. Dual indentical logic circuits are employed wherein each of the circuits include error circuit elements that are coupled to receive the interrupt signal and arithmetic sequence initiation signals. A comparator is coupled to an output of each of the dual identical logic circuit to receive signals that are used to indicate when an interrupt signal and an arithmetic sequence initiation signal occurs simultaneously in only one of the logic circuits. Clear sequence circuitry in each of the dual identical logic circuits receives the interrupt signal and selectively supplies clear signals to the logic elements.
摘要翻译： 用于数据处理系统的指令处理器运行由序列指示符信号启动并被中断信号中断的算术序列。 在处理器的操作期间，在发生中断信号之后，序列指示符信号处于非活动状态的时间期间，处理器的逻辑元件被清除信号选择性地清除。 采用双重逻辑逻辑电路，其中每个电路包括耦合以接收中断信号的误差电路元件和算术序列起始信号。 比较器耦合到双相同逻辑电路中的每一个的输出，以接收用于指示何时中断信号和算术序列起始信号同时出现在仅一个逻辑电路中的信号。 每个双相同逻辑电路中的清除序列电路接收中断信号，并且有选择地向逻辑元件提供清除信号。
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公开(公告)号：US4989172A
公开(公告)日：1991-01-29
申请号：US475610
申请日：1990-02-06
申请人： Peter B. Criswell
发明人： Peter B. Criswell
IPC分类号： G06F11/00
CPC分类号： G06F11/0751
摘要： Apparatus for checking and detecting erroneous start signals is provided in the arithmetic section of a high speed instruction processor and may be embodied in other types of processors. The novel logic circuits include circuits for detecting an attempted start signal while a previous instruction is still in process; logic circuits for detecting when an even arithmetic sequence and an odd arithmetic sequence other than the first sequence are being concurrently processed; and logic circuits for detecting when an AR start instruction is being attempted during a wrong minor cycle.
摘要翻译： 用于检查和检测错误启动信号的装置设置在高速指令处理器的运算部分中，并且可以体现在其它类型的处理器中。 新颖的逻辑电路包括用于在先前指令仍在进行中时检测尝试启动信号的电路; 用于检测偶数算术序列和除第一序列之外的奇数运算顺序同时被处理的逻辑电路; 以及用于在错误的次要周期期间检测何时正在尝试AR启动指令的逻辑电路。
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10.发明授权公开(公告)号：US07451270B1
公开(公告)日：2008-11-11
申请号：US10675841
申请日：2003-09-30
申请人： Peter B. Criswell
发明人： Peter B. Criswell
IPC分类号： G06F12/00
CPC分类号： G06F11/1052
摘要： A system and method for detecting and correcting errors within a control system is disclosed. A storage device stores data values that are used to control one or more circuits within the system. This storage device may operate as a slave, such that the storage device is addressed using address signals provided by an external source. This storage device may also operate as master such that some of the data signals that are read from the storage device are used to generate the address for performing the next reference the storage device. In the former slave scenario, and in some cases wherein the storage device is operating as a master, data signals that would otherwise be employed to generate an address are instead employed as check bits to implement an error detection and correction scheme.
摘要翻译： 公开了一种用于检测和校正控制系统内的错误的系统和方法。 存储设备存储用于控制系统内的一个或多个电路的数据值。 该存储设备可以作为从设备操作，使得使用由外部源提供的地址信号来寻址存储设备。 该存储装置还可以作为主机操作，使得从存储装置读取的一些数据信号用于生成用于执行下一个参考的存储装置的地址。 在前一个业务情景中，在存储设备作为主设备运行的一些情况下，否则将采用生成地址的数据信号作为校验位来执行错误检测和校正方案。
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