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公开(公告)号：US4595911A
公开(公告)日：1986-06-17
申请号：US514208
申请日：1983-07-14
CPC分类号： G06F9/30025 , G06F5/012 , G06F9/30036 , G06F9/30167
摘要： A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.
摘要翻译： 描述了利用可编程控制的多路复用器级别的高速系统，用于将数据从可编程选择的第一格式重新格式化为第二格式。 利用交错的输入数据优化重新格式化速率。 重新格式化系统提供了现场选择和理由，以及所选领域的补充和量产能力。 可以解包两种不同浮点格式的浮点操作数，即从尾数分离的特性和正确对齐的特征，并且可以通过将特征与相关尾数进行定位和重组来进行打包。 在整个重新格式化过程中，维持所选位分组的奇偶校验，从而允许通过检查重新格式化操作。 重新格式化系统包括可编程选择的恒定生成。
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公开(公告)号：US4556978A
公开(公告)日：1985-12-03
申请号：US515401
申请日：1983-07-20
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.
摘要翻译： 公开了适用于门阵列中的LSI实现的72位移位矩阵。 8字节移位器和8位移位器被组合以产生0-72个位置的方向，圆形或开放的零位或符号填充位移。 另外提供了一种装置，用于从矩阵输出再生原始源奇偶校验以用于通过检查。 单个9位奇偶校验发生器是检查矩阵正确性所需要的。
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3.发明授权Storage locking control for a plurality of processors which share a common storage unit 失效共享公共存储单元的多个处理器的存储锁定控制
公开(公告)号：US4984153A
公开(公告)日：1991-01-08
申请号：US186827
申请日：1988-04-27
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F12/00 , G06F15/177
CPC分类号： G06F9/52
摘要： In a plural processor data processing system, a lock is obtained on a commonly shared storage means that allows for the testing of a control word associated with a selected memory address of a particular data processor wherein each of the data processors of the system is capable of independently requesting a lock on said control word. Lock requests are broadcast to each of the data processors. The lock is then established according to predefined criteria by transmission of the lock requests of all of said processor means at the same time at controlled intervals, and by providing the lock on the control word when the requesting processor is the only processor that is requesting a given control word during a control interval, or when the processor transmits its lock request simultaneously with other processor means of a lower priority.
摘要翻译： 在多处理器数据处理系统中，在公共共享存储装置上获得锁，其允许测试与特定数据处理器的选定存储器地址相关联的控制字，其中系统的每个数据处理器能够 独立地请求锁定所述控制字。 锁定请求被广播到每个数据处理器。 然后根据预定义的标准通过以受控的间隔同时发送所有所述处理器装置的锁定请求来建立锁定，并且当请求处理器是请求处理器的唯一处理器时通过向控制字提供锁定 在控制间隔期间，或者当处理器与较低优先级的其他处理器装置同时发送其锁定请求时给定控制字。
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公开(公告)号：US4366548A
公开(公告)日：1982-12-28
申请号：US221981
申请日：1981-01-02
CPC分类号： G06F7/502 , G06F7/485 , G06F7/508 , G06F9/30014 , G06F9/30036 , G06F2207/382 , G06F2207/3836 , G06F7/4991
摘要： A characteristic adder for use in a data processing system that performs floating-point arithmetic operations is described. A 1's complement subtractive adder is shown for forming the sum or difference of a pair of exponents under control of function control circuitry, along with an indication of which characteristic is larger for selecting which mantissa operand should be shifted for proper alignment. The function control circuitry responds to function signals to select addition or subtraction, provide the magnitude or complement of the results, and select between two available floating-point formats. Characteristic Overflow and Underflow is tested and signaled for each of the two possible floating-point formats.
摘要翻译： 描述用于执行浮点算术运算的数据处理系统中的特征加法器。 示出了1的补码减法加法器，用于在功能控制电路的控制下形成一对指数的和或差，以及哪个特性较大的指示，用于选择哪个尾数操作数应被移位以进行适当的对准。 功能控制电路响应功能信号选择加法或减法，提供结果的大小或互补，并在两种可用的浮点格式之间进行选择。 针对两种可能的浮点格式中的每一种测试特征溢出和下溢信号。
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公开(公告)号：US4592005A
公开(公告)日：1986-05-27
申请号：US395519
申请日：1982-07-06
申请人： Glen R. Kregness
发明人： Glen R. Kregness
CPC分类号： G06F7/57 , G06F7/48 , G06F7/507 , G06F7/508 , G06F2207/3836
摘要： An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares and mask substitute operations without adding logic levels to the arithmetic logic unit; (2) the inclusion of a sum minus one network to speed up system performance by minimizing the delay usually associated with group borrow input to final sum output and (3) the inclusion of a mode control register internal to the arithmetic logic unit to minimize or camouflage the delay always found in the mode switching control of contemporary arithmetic logic units.
摘要翻译： 公开了一种改进的掩蔽算术逻辑单元，其包括至少三个主要的独特特征以优化在高速环境中的实现。 这些特征是（1）包括掩码操作数以便于掩码比较和掩码替代操作，而不向算术逻辑单元添加逻辑电平; （2）包括一个减去一个网络的总和，通过最小化通常与组合借位输入与最终和输出相关联的延迟来加快系统性能，以及（3）在算术逻辑单元内部包括模式控制寄存器以使 伪装在当代算术逻辑单元的模式切换控制中总是发现的延迟。
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6.发明授权Apparatus and method for controlling exclusive access to portions of addressable memory in a multiprocessor system 失效用于控制在多处理器系统中对可寻址存储器的部分的独占访问的装置和方法
公开(公告)号：US5408629A
公开(公告)日：1995-04-18
申请号：US929329
申请日：1992-08-13
CPC分类号： G06F9/52 , G06F13/18 , G06F12/0815
摘要： A method and apparatus for granting exclusive access to a selected portion of addressable memory to a requesting processor in a large scale multiprocessor system. An instruction processor having a store-through operand cache executes an instruction requiring exclusive access to an address in a shared memory. If the address upon which the lock is requested is not in the local cache, the instruction processor simultaneously sends a lock and read request to the coupled storage controller. Otherwise, a no-operand-read and lock request is sent to the storage controller. If, while processing the lock request, no conflict is detected by the storage controller, the address is marked as locked and a lock granted signal is issued to the requesting processor. Concurrent with the processing the lock request the storage controller processes the read request. The lock granted signal and requested data are returned to the requesting processor asynchronously. The requesting processor can continue processing the lock instruction when the lock granted and required data have been returned from the storage controller. When two or more processors contend for a lock on a the same portion of addressable memory, one processor is granted the lock while the other contending processor(s) are forced to wait. Lock contention is arbitrated by a round robin priority scheme.
摘要翻译： 一种用于向大规模多处理器系统中的请求处理器授予对可寻址存储器的选定部分的独占访问的方法和装置。 具有存储操作数高速缓存的指令处理器执行需要对共享存储器中的地址的独占访问的指令。 如果要求锁定的地址不在本地高速缓存中，则指令处理器同时向耦合的存储控制器发送锁定和读取请求。 否则，将无操作数读取和锁定请求发送到存储控制器。 如果在处理锁定请求时，存储控制器没有检测到冲突，则该地址被标记为锁定，并且向请求处理器发出锁定授权信号。 与处理锁请求同时存储控制器处理读请求。 锁定信号和请求的数据被异步地返回给请求处理器。 当已经从存储控制器返回已授予的锁定和所需数据时，请求处理器可以继续处理锁定指令。 当两个或更多个处理器在可寻址存储器的相同部分上进行锁定时，一个处理器被授予锁定，而另一个竞争处理器被迫等待。 锁定争用由循环优先级方案仲裁。
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公开(公告)号：US4875180A
公开(公告)日：1989-10-17
申请号：US192081
申请日：1988-05-09
IPC分类号： G06F5/01
CPC分类号： G06F5/015
摘要： A left justification scale factor generator is described which is capable of scaling numbers for binary number groups off one, two, three and four bit groups. Two basic building block circuits are utilized in the scale factor generator's priority encoder, which looks at four binary bits and produces a two bit binary count that corresponds to the first non-zero input found, and an algebraic priority encoder which also receives a reference signal that allows it to indicate the significance of the priority detection level. By sensing correction factors at the first level of the system, the number of logic levels are kept to a minimum.
摘要翻译： 描述了一个左对齐比例因子发生器，其能够缩小从一个，两个，三个和四个位组的二进制数组的数字。 在比例因子发生器的优先级编码器中使用两个基本构建块电路，其中查看四个二进制位并且产生对应于找到的第一非零输入的二位二进制计数，以及也接收参考信号的代数优先级编码器 这允许它指示优先级检测级别的重要性。 通过感测系统第一级的校正因子，将逻辑电平的数量保持在最小。
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公开(公告)号：US4523210A
公开(公告)日：1985-06-11
申请号：US387644
申请日：1982-06-11
申请人： Glen R. Kregness
发明人： Glen R. Kregness
CPC分类号： G06F7/5312 , G06F11/10
摘要： A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder array to eliminate the decoding of multiplier characters thereby reducing logic levels and enhancing performance. A means is illustrated for detecting single bit errors without redundancy or performance loss. While the array proper is more complex than other multibit algorithms, the multiplexers needed by those earlier systems are no longer required. The small increase in complexity of the array proper eliminates the need for decoding of the multiplier bits or other interaction between the multiplier groups. The net effect is a reduction in logic with faster operation because of the omission of the decoding requirement.
摘要翻译： 公开了一种高速乘法器电路，其不仅为大规模处理器的乘法运算提供增加的性能，而且还提供结果的单位错误检测。 它集成了门控进位/保存加法器阵列，以消除乘法器字符的解码，从而降低逻辑电平并提高性能。 示出了用于检测单个位错误而没有冗余或性能损失的装置。 虽然阵列本身比其他多位算法更复杂，但是不再需要这些早期系统所需的多路复用器。 阵列恰当的复杂度的小幅增加消除了对乘法器位的解码或乘法器组之间的其他交互的需要。 净效应是由于省略了解码要求而使操作更快的逻辑减少。
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