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    Memory structure with self-adjusting capacitive coupling-based read and write assist
    1.
    发明授权
    Memory structure with self-adjusting capacitive coupling-based read and write assist 有权

    公开(公告)号：US11900996B2

    公开(公告)日：2024-02-13

    申请号：US17504558

    申请日：2021-10-19

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Bhuvan R. Nandagopal ,  Shivraj G. Dharne

    IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

    Abstract: Disclosed is a memory structure that includes wordlines (WL) and cell supply lines (CSL) positioned between and parallel to voltage boost lines (VBLs). The VBLs enable capacitive coupling-based voltage boosting of the adjacent WL and/or CSL depending on whether a read or write assist is required. During a read operation, all VBLs for a selected row can be charged to create coupling capacitances with the WL and with the CSL and thereby boost both the wordline voltage (Vwl) and the cell supply voltage (Vcs) for a read assist. During a write operation, one VBL adjacent to the WL for a selected row can be charged to create a coupling capacitance with the WL only and thereby boost the Vwl for a write assist. The coupling capacitances created by charging VBLs in the structure is self-adjusting in that as the length of the rows increase so do the potential coupling capacitances.

    Output buffer circuit
    2.
    发明授权
    Output buffer circuit 有权

    公开(公告)号：US12047068B2

    公开(公告)日：2024-07-23

    申请号：US18080378

    申请日：2022-12-13

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Dzung T. Tran ,  Shivraj G. Dharne

    IPC: H03K19/01 ,  H03K19/003 ,  H03K19/0185

    CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/00361

    Abstract: The present disclosure relates to a structure including a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal, a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit including at least one delay circuit, and a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal.

    Single-rail memory circuit with row-specific voltage supply lines and boost circuits
    3.
    发明授权
    Single-rail memory circuit with row-specific voltage supply lines and boost circuits 有权

    公开(公告)号：US11322200B1

    公开(公告)日：2022-05-03

    申请号：US17120325

    申请日：2020-12-14

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

    IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

    Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.

    CIRCUIT AND METHOD FOR START-UP OF REFERENCE CIRCUITS IN DEVICES WITH A PLURALITY OF SUPPLY VOLTAGES
    5.
    发明公开
    CIRCUIT AND METHOD FOR START-UP OF REFERENCE CIRCUITS IN DEVICES WITH A PLURALITY OF SUPPLY VOLTAGES 审中-公开

    公开(公告)号：US20240275282A1

    公开(公告)日：2024-08-15

    申请号：US18166576

    申请日：2023-02-09

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Dzung T. TRAN ,  Shivraj G. Dharne ,  Asif Iqbal

    IPC: H02M3/158 ,  H02M1/00 ,  H02M1/096 ,  H02M1/36

    CPC classification number: H02M3/158 ,  H02M1/0009 ,  H02M1/096 ,  H02M1/36

    Abstract: A reference circuit for an electronic device having a plurality of power supply voltages comprises a supply start-up circuit, a power-down start-up circuit, and a reference generating circuit. The supply start-up circuit comprising a resistive-capacitive (RC) circuit coupled between a first power supply voltage and a ground. The RC circuit includes a pulse node coupled between a first capacitor and a resistive element, and generates a power-up pulse signal at the pulse node. The power-down start-up circuit is powered by a second power supply voltage and comprises a pulse generation circuit that generates a first start-up signal. The reference generating circuit outputs a reference signal. The reference generating circuit exists a low-power mode when either of the power-up pulse signal and the first start-up signal is generated.

    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS
    6.
    发明公开
    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS 审中-公开

    公开(公告)号：US20230341888A1

    公开(公告)日：2023-10-26

    申请号：US17726171

    申请日：2022-04-21

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

    IPC: G06F1/10 ,  G06F15/78

    CPC classification number: G06F1/10 ,  G06F15/7839

    Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

    LOW-LEAKAGE SENSE CIRCUIT, MEMORY CIRCUIT INCORPORATING THE LOW-LEAKAGE SENSE CIRCUIT, AND METHOD
    7.
    发明申请
    LOW-LEAKAGE SENSE CIRCUIT, MEMORY CIRCUIT INCORPORATING THE LOW-LEAKAGE SENSE CIRCUIT, AND METHOD 有权

    公开(公告)号：US20220215872A1

    公开(公告)日：2022-07-07

    申请号：US17143193

    申请日：2021-01-07

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Shivraj G. Dharne ,  Uttam K. Saha ,  Mahbub Rashed

    IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

    Abstract: A disclosed sense circuit for a memory circuit includes sense amplifiers that detect differences in voltage levels on complementary bitlines during read operations. Instead of the sense amplifiers having built-in footer devices that lead to significant leakage, the sense circuit incorporates a common footer device for all sense amplifiers. To ensure that this footer device has sufficient drive strength to enable voltage differential detection by each sense amplifier, the sense circuit also includes a sense signal generation and boost circuit (SSG&B circuit) that generates a sense mode control signal (SEN) to control the on/off states of the footer device and that further boosts SEN, at the appropriate time, to increase the drive current. By using the common footer device and the SSG&B circuit, leakage from the sense circuit is reduced during a pre-charge operation mode without sacrificing performance during a read operation mode. Also disclosed are associated method embodiments.

    Low-leakage row decoder and memory structure incorporating the low-leakage row decoder
    8.
    发明授权
    Low-leakage row decoder and memory structure incorporating the low-leakage row decoder 有权

    公开(公告)号：US11769545B2

    公开(公告)日：2023-09-26

    申请号：US17498788

    申请日：2021-10-12

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Vinayak R. Ganji ,  Shivraj G. Dharne

    IPC: G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

    CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096

    Abstract: Disclosed are embodiments of a low-leakage row decoder and a memory circuit incorporating the row decoder. The row decoder includes wordline driver circuitry including first devices (pre-drivers) and second devices (wordline drivers). Each second device is connected in series between a first device and a wordline for a row in a memory array. The first devices can be directly connected to a positive supply voltage rail and connected to a ground rail through a footer. The second devices can be connected to the positive supply voltage rail through a header and directly connected to the ground rail. The on/off states of the header and footer are controlled by clock signal-dependent control signals so that they are either concurrently on or off. With this configuration, leakage power consumption of the wordline driver circuitry is minimized while the memory structures as idle and also while it operates in a normal active mode.

    MEMORY STRUCTURE WITH SELF-ADJUSTING CAPACITIVE COUPLING-BASED READ AND WRITE ASSIST
    9.
    发明申请
    MEMORY STRUCTURE WITH SELF-ADJUSTING CAPACITIVE COUPLING-BASED READ AND WRITE ASSIST 有权

    公开(公告)号：US20230122564A1

    公开(公告)日：2023-04-20

    申请号：US17504558

    申请日：2021-10-19

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Bhuvan R. Nandagopal ,  Shivraj G. Dharne

    IPC: G11C11/419 ,  G11C11/412 ,  G11C11/418

    Abstract: Disclosed is a memory structure that includes wordlines (WL) and cell supply lines (CSL) positioned between and parallel to voltage boost lines (VBLs). The VBLs enable capacitive coupling-based voltage boosting of the adjacent WL and/or CSL depending on whether a read or write assist is required. During a read operation, all VBLs for a selected row can be charged to create coupling capacitances with the WL and with the CSL and thereby boost both the wordline voltage (Vwl) and the cell supply voltage (Vcs) for a read assist. During a write operation, one VBL adjacent to the WL for a selected row can be charged to create a coupling capacitance with the WL only and thereby boost the Vwl for a write assist. The coupling capacitances created by charging VBLs in the structure is self-adjusting in that as the length of the rows increase so do the potential coupling capacitances.

    LOW-LEAKAGE ROW DECODER AND MEMORY STRUCTURE INCORPORATING THE LOW-LEAKAGE ROW DECODER
    10.
    发明申请
    LOW-LEAKAGE ROW DECODER AND MEMORY STRUCTURE INCORPORATING THE LOW-LEAKAGE ROW DECODER 有权

    公开(公告)号：US20230115230A1

    公开(公告)日：2023-04-13

    申请号：US17498788

    申请日：2021-10-12

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Vivek Raj ,  Vinayak R. Ganji ,  Shivraj G. Dharne

    IPC: G11C11/408 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4096

    Abstract: Disclosed are embodiments of a low-leakage row decoder and a memory circuit incorporating the row decoder. The row decoder includes wordline driver circuitry including first devices (pre-drivers) and second devices (wordline drivers). Each second device is connected in series between a first device and a wordline for a row in a memory array. The first devices can be directly connected to a positive supply voltage rail and connected to a ground rail through a footer. The second devices can be connected to the positive supply voltage rail through a header and directly connected to the ground rail. The on/off states of the header and footer are controlled by clock signal-dependent control signals so that they are either concurrently on or off. With this configuration, leakage power consumption of the wordline driver circuitry is minimized while the memory structures as idle and also while it operates in a normal active mode.

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