公开(公告)号：US11335674B2

公开(公告)日：2022-05-17

申请号：US16455071

申请日：2019-06-27

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Souvick Mitra ,  Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  You Li ,  Tsung-Che Tsai

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

公开(公告)号：US11171132B2

公开(公告)日：2021-11-09

申请号：US16592013

申请日：2019-10-03

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  You Li ,  Tsung-Che Tsai

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/747 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.

公开(公告)号：US11791626B2

公开(公告)日：2023-10-17

申请号：US17490371

申请日：2021-09-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Mickey Yu ,  Robert J. Gauthier, Jr.

IPC: H02H9/04 ,  H01L27/02 ,  H02H1/00 ,  H01L23/60

CPC classification number: H02H9/046 ,  H01L23/60 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0288 ,  H01L27/0292 ,  H02H1/0007

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

公开(公告)号：US20220037309A1

公开(公告)日：2022-02-03

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

公开(公告)号：US11769767B2

公开(公告)日：2023-09-26

申请号：US17704422

申请日：2022-03-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Souvick Mitra ,  Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  You Li ,  Tsung-Che Tsai

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0262

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

公开(公告)号：US20220320073A1

公开(公告)日：2022-10-06

申请号：US17808647

申请日：2022-06-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, JR. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

公开(公告)号：US11289471B2

公开(公告)日：2022-03-29

申请号：US17001009

申请日：2020-08-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Robert J. Gauthier, Jr. ,  Meng Miao

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/73 ,  H01L27/06 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

公开(公告)号：US11201466B2

公开(公告)日：2021-12-14

申请号：US16033731

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： You Li ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Mickey Yu ,  Robert J. Gauthier, Jr.

IPC: H02H9/04 ,  H01H1/00 ,  H01L23/60 ,  H01L27/02 ,  H02H1/00

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

公开(公告)号：US12068308B2

公开(公告)日：2024-08-20

申请号：US17808647

申请日：2022-06-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0255

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a triple well structure within a semiconductor substrate. A base region is within a doped well of the triple well structure, a collector terminal is within the doped well and laterally separated from the base region by a first insulator and a first avalanche junction is defined between a first pair of oppositely-doped semiconductor regions within the collector terminal. An emitter terminal is within the third doped well of the triple well structure and laterally separated from the collector terminal by a second insulator. A second avalanche junction is defined between a second pair of oppositely-doped semiconductor regions of the emitter terminal.

公开(公告)号：US11444076B2

公开(公告)日：2022-09-13

申请号：US16983071

申请日：2020-08-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Alain F. Loiseau ,  Souvick Mitra ,  Tsung-Che Tsai ,  Meng Miao ,  You Li

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.