公开(公告)号：US20070183234A1

公开(公告)日：2007-08-09

申请号：US11527088

申请日：2006-09-26

申请人： Gong-Heum Han ,  Chul-Sung Park ,  Hyung-Jin Kim ,  Byeong-Uk Yoo

发明人： Gong-Heum Han ,  Chul-Sung Park ,  Hyung-Jin Kim ,  Byeong-Uk Yoo

IPC分类号： G11C7/00

CPC分类号： G11C11/413

摘要： An enhanced semiconductor memory device capable of eliminating or minimizing a cell data flip phenomenon caused by capacitive voltage coupling between bit lines in different bit line pairs. Each memory cell is connected to a word line and between a pair of bit line. A first precharging and equalizing circuit us connected to a first bit line pair and a second precharging and equalizing circuit us connected to an adjacent second bit line pair. The first and second precharging and equalizing circuit are activated independently and at different times in order to reduce voltage coupling between neighboring bit lines in different bit line pairs, thereby minimizing or eliminating a cell data flip phenomenon of a neighboring memory cell caused by voltage coupling between bit lines.

摘要翻译： 一种增强的半导体存储器件，其能够消除或最小化由不同位线对中的位线之间的电容电压耦合引起的单元数据翻转现象。 每个存储单元连接到字线和一对位线之间。 我们连接到第一位线对的第一个预充电和均衡电路，以及连接到相邻的第二位线对的第二个预充电和均衡电路。 第一和第二预充电和均衡电路在不同时间独立激活，以便减少不同位线对中的相邻位线之间的电压耦合，从而最小化或消除由相邻存储器单元之间的电压耦合引起的单元数据翻转现象 位线。

公开(公告)号：US07221611B2

公开(公告)日：2007-05-22

申请号：US11146513

申请日：2005-06-07

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Joon-Min Park

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C11/417 ,  G11C5/147

摘要： A semiconductor memory device, which has an array of memory cells connected with a plurality of bit line pairs and a plurality of word lines, to perform a read or write operation of data, having low power consumption is provided. The device includes a first power supply for supplying a first power source voltage. Also, a second power supply supplies a second power source voltage having a lower voltage level than the first power source voltage. Further, the device includes a standard ground. An elevated ground circuit provides an elevated ground voltage having a higher voltage level than that of the standard ground. A first power circuit is connected with the first power supply and the standard ground, and operates in response to the first power source voltage. A second power circuit is connected with the second power supply and the elevated ground circuit, and operates in response to the second power source voltage. Thereby, power and chip size can be reduced.

摘要翻译： 提供具有与多个位线对和多个字线连接的存储单元的阵列以执行具有低功耗的数据的读取或写入操作的半导体存储器件。 该装置包括用于提供第一电源电压的第一电源。 此外，第二电源提供具有比第一电源电压低的电压电平的第二电源电压。 此外，该装置包括标准接地。 提升的接地电路提供比标准接地电压高的电压电平的升高的接地电压。 第一电源电路与第一电源和标准接地相连接，并响应于第一电源电压而工作。 第二电源电路与第二电源和升高的接地电路连接，并且响应于第二电源电压而工作。 从而可以降低功率和芯片尺寸。

公开(公告)号：US20090294863A1

公开(公告)日：2009-12-03

申请号：US12537521

申请日：2009-08-07

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L29/66

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US07315466B2

公开(公告)日：2008-01-01

申请号：US11191496

申请日：2005-07-28

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US20060157737A1

公开(公告)日：2006-07-20

申请号：US11326159

申请日：2006-01-05

申请人： Bo-Tak Lim ,  Su-Yeon Kim ,  Jong-Pil Son ,  Gong-Heum Han

发明人： Bo-Tak Lim ,  Su-Yeon Kim ,  Jong-Pil Son ,  Gong-Heum Han

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： A semiconductor memory device comprises a cell region including a plurality of unit memory cells, and a peripheral circuit region, the peripheral circuit region including a plurality of peripheral circuit devices for operating the plurality of memory cells and at least one operating capacitor formed adjacent to at least one peripheral circuit device at a pseudo circuit pattern region.

摘要翻译： 一种半导体存储器件包括一个包括多个单元存储单元的单元区域和一个外围电路区域，该外围电路区域包括用于操作该多个存储单元的多个外围电路器件以及邻近形成的至少一个工作电容器 在伪电路图案区域中的至少一个外围电路器件。

公开(公告)号：US07982221B2

公开(公告)日：2011-07-19

申请号：US12537521

申请日：2009-08-07

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L29/76

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US20080165603A1

公开(公告)日：2008-07-10

申请号：US11969947

申请日：2008-01-07

申请人： Gong-Heum Han

发明人： Gong-Heum Han

IPC分类号： G11C7/00

CPC分类号： G11C7/065

摘要： A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns, a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier, and a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch type mode after the predetermined period.

摘要翻译： 半导体存储器件包括存储单元阵列，具有以行和列排列的存储单元，行解码器选择行中的一个并激活所选择的行，位线读出放大器检测和放大耦合到所选择的存储单元的数据 通过列排列的数据总线读出放大器，检测和放大从位线读出放大器输出的数据;以及控制逻辑块，使读取操作中的位线和数据总线读出放大器工作，操作数据总线 在预定时间段内以半锁存型模式读出放大器，并且在预定时间段之后以全锁存类型模式操作数据总线读出放大器。

公开(公告)号：US06714463B2

公开(公告)日：2004-03-30

申请号：US10251739

申请日：2002-09-20

申请人： Gong-Heum Han ,  Choong-Keun Kwak ,  Kyeong-Yoon Bae

发明人： Gong-Heum Han ,  Choong-Keun Kwak ,  Kyeong-Yoon Bae

IPC分类号： G11C700

CPC分类号： G11C8/18 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2281

摘要： A semiconductor memory device is provided to generate a series of pulse signals in response to the activation of an internal chip select signal from an internal chip select buffer when an external chip select signal transitions from an inactive state to an active state. With this configuration, a chip select output time (tco) is more reduced as compared to prior arts. Further, the chip select output time is reduced to be equal to an address access time (tAA) because a designer can control the chip select output time. As a result, the whole access time of the semiconductor memory device can be reduced.

摘要翻译： 半导体存储器件被提供以当外部芯片选择信号从非活动状态转换到激活状态时，响应于来自内部芯片选择缓冲器的内部芯片选择信号的激活而产生一系列脉冲信号。 利用这种配置，与现有技术相比，芯片选择输出时间（tco）更多地减少。 此外，芯片选择输出时间减小到等于地址访问时间（tAA），因为设计者可以控制芯片选择输出时间。 结果，可以减少半导体存储器件的整个访问时间。

公开(公告)号：US07596044B2

公开(公告)日：2009-09-29

申请号：US11969947

申请日：2008-01-07

申请人： Gong-Heum Han

发明人： Gong-Heum Han

IPC分类号： G11C7/00

CPC分类号： G11C7/065

摘要： A semiconductor memory device includes a memory cell array having memory cells arranged in rows and columns, a row decoder selecting one of the rows and activating the selected row, a bit-line sense amplifier detecting and amplifying data of the memory cells coupled to the selected row through the columns, a data-bus sense amplifier detecting and amplifying data output from the bit-line sense amplifier, and a control logic block enabling the bit-line and data-bus sense amplifiers in a reading operation, operating the data-bus sense amplifier in a semi-latch type mode for a predetermined period, and operating the data-bus sense amplifier in a full-latch type mode after the predetermined period.

摘要翻译： 半导体存储器件包括存储单元阵列，具有以行和列排列的存储单元，行解码器选择行中的一个并激活所选择的行，位线读出放大器检测和放大耦合到所选择的存储单元的数据 通过列排列的数据总线读出放大器，检测和放大从位线读出放大器输出的数据;以及控制逻辑块，使读取操作中的位线和数据总线读出放大器工作，操作数据总线 在预定时间段内以半锁存型模式读出放大器，并且在预定时间段之后以全锁存类型模式操作数据总线读出放大器。

公开(公告)号：US07589992B2

公开(公告)日：2009-09-15

申请号：US11953289

申请日：2007-12-10

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。