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    Rate Update Engine For Reliable Transport Protocol
    3.
    发明申请
    Rate Update Engine For Reliable Transport Protocol 有权

    公开(公告)号：US20210399990A1

    公开(公告)日：2021-12-23

    申请号：US16907423

    申请日：2020-06-22

    Applicant: Google LLC

    Inventor： Xiaoming Wang ,  Prashant Chandra ,  Neelesh Bansod ,  Nandita Dukkipati ,  Hassan Wassel ,  Gautam Kumar ,  Weihuang Wang ,  Michael Marty ,  Nicholas McDonald

    IPC: H04L12/825 ,  H04L12/801 ,  H04L12/863

    Abstract: A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.

    Fault Tolerant Design For Clock-Synchronization Systems
    4.
    发明申请
    Fault Tolerant Design For Clock-Synchronization Systems 有权

    公开(公告)号：US20210320736A1

    公开(公告)日：2021-10-14

    申请号：US17091158

    申请日：2020-11-06

    Applicant: Google LLC

    Inventor： Yuliang Li ,  Gautam Kumar ,  Nandita Dukkipati ,  Hassan Wassel ,  Prashant Chandra ,  Amin Vahdat

    IPC: H04J3/06 ,  H04L7/00 ,  H04L12/44

    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

    Fault tolerant design for clock-synchronization systems
    5.
    发明授权
    Fault tolerant design for clock-synchronization systems 有权

    公开(公告)号：US11799577B2

    公开(公告)日：2023-10-24

    申请号：US17891215

    申请日：2022-08-19

    Applicant: Google LLC

    Inventor： Yuliang Li ,  Gautam Kumar ,  Nandita Dukkipati ,  Hassan Wassel ,  Prashant Chandra ,  Amin Vahdat

    IPC: H04J3/06 ,  H04L7/00 ,  H04L12/44

    CPC classification number: H04J3/0641 ,  H04J3/065 ,  H04L7/0016 ,  H04L12/44

    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

    Fault Tolerant Design For Clock-Synchronization Systems
    7.
    发明申请
    Fault Tolerant Design For Clock-Synchronization Systems 有权

    公开(公告)号：US20220393783A1

    公开(公告)日：2022-12-08

    申请号：US17891215

    申请日：2022-08-19

    Applicant: Google LLC

    Inventor： Yuliang Li ,  Gautam Kumar ,  Nandita Dukkipati ,  Hassan Wassel ,  Prashant Chandra ,  Amin Vahdat

    IPC: H04J3/06 ,  H04L7/00 ,  H04L12/44

    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

    Network Congestion Control In Sub-Round Trip Time
    9.
    发明公开
    Network Congestion Control In Sub-Round Trip Time 审中-公开

    公开(公告)号：US20230336490A1

    公开(公告)日：2023-10-19

    申请号：US18136551

    申请日：2023-04-19

    Applicant: Google LLC

    Inventor： Serhat Arslan ,  Yuliang Li ,  Gautam Kumar ,  Nandita Dukkipati

    IPC: H04L47/27 ,  H04L47/12 ,  H04L47/30 ,  H04L47/215

    CPC classification number: H04L47/27 ,  H04L47/12 ,  H04L47/30 ,  H04L47/215

    Abstract: Aspects of the disclosure provide for congestion control mechanisms to reduce data transmission queues and to increase link utilization through precise congestion signals and reduction of control loop delay. A congestion control system (CC) system can utilize Back-To-Sender (BTS) packets over (round trip time) RTT control loop delay to react to congestion faster. The CC system can apply Proactive Ramp-up (PRU) to identify flow completions to occupy released bandwidth right on time, e.g., as bandwidth is made available. The CC system can perform supply matching (SM) through network calculus concepts to increase link utilization. The CC system can apply some or all of the use of BTS packets, PRU, and/or SM to reduce network latency and improve data flow completion time as compared with other approaches.

    Fault tolerant design for clock-synchronization systems
    10.
    发明授权
    Fault tolerant design for clock-synchronization systems 有权

    公开(公告)号：US11463187B2

    公开(公告)日：2022-10-04

    申请号：US17091158

    申请日：2020-11-06

    Applicant: Google LLC

    Inventor： Yuliang Li ,  Gautam Kumar ,  Nandita Dukkipati ,  Hassan Wassel ,  Prashant Chandra ,  Amin Vahdat

    IPC: H04J3/06 ,  H04L7/00 ,  H04L12/44

    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

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