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1.发明授权Method and system for automatically determining data communication device type and corresponding transmission rate 失效自动确定数据通信设备类型和相应传输速率的方法和系统
公开(公告)号：US5491720A
公开(公告)日：1996-02-13
申请号：US887433
申请日：1992-05-21
申请人： Gordon T. Davis , Judith M. Linger , Baiju D. Mandalia , John C. Sinibaldi , William M. Zevin , Karl-Heinz Ziegenhain
发明人： Gordon T. Davis , Judith M. Linger , Baiju D. Mandalia , John C. Sinibaldi , William M. Zevin , Karl-Heinz Ziegenhain
CPC分类号： H04L29/06 , H04L25/0262 , H04L27/0012 , H04L69/18
摘要： A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals. Utilizing the relationship between the response signal and the transmitted sequence of different signals, a data communication device type and transmission speed are determined, and data communications may then be established between the first data communication device and the second data communication device at an optimal transmission speed.
摘要翻译： 一种用于自动确定与数据通信设备类型相关联的数据通信设备类型和传输速度的数据通信系统中的方法和系统。 在传输线上检测到进入通信，并且发送和接收硬件连接到传输线。 接下来，通过传输线从第一数据通信设备发送第一通信协议或第二通信协议中的不同信号的序列。 然后监测传输线路的来自第二数据通信设备的响应信号。 响应于响应于在所发送的不同信号序列内的特定信号的接收，响应信号从第二数据通信设备发起。 利用响应信号和不同信号的发送序列之间的关系，确定数据通信设备类型和传输速度，然后可以以最佳传输速度在第一数据通信设备和第二数据通信设备之间建立数据通信 。
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2.发明授权Method and system for interpolating baud rate timing recovery for asynchronous start stop protocol 失效用于内插异步启动停止协议的波特率定时恢复的方法和系统
公开(公告)号：US5263054A
公开(公告)日：1993-11-16
申请号：US886674
申请日：1992-05-21
CPC分类号： H04L25/05
摘要： An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.
摘要翻译： 一种用于对采样信号的数字信号处理器进行解调处理的有效计算的装置，其包括对数字信号处理器进行编程以将采样信号施加到内插滤波器以将采样信号加到采样信号中， 与开始位相关联的阈值交叉，执行线性内插，以在检测到阈值交叉时发现阈值交叉发生的点，响应于确定阈值交叉点，确定起点的中心，当点 已经确定了阈值交叉，计算补充延迟，并且利用来自起始位的中心的补充延迟周期来确定随后的数据位的中心点。
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3.发明授权公开(公告)号：US08400845B2
公开(公告)日：2013-03-19
申请号：US12985481
申请日：2011-01-06
申请人： Lydia M. Do , William M. Zevin
发明人： Lydia M. Do , William M. Zevin
IPC分类号： G11C7/10
CPC分类号： G11C11/4076 , G06F13/1689 , G11C8/18 , G11C11/406 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.
摘要翻译： 列地址选通写延迟（CWL）校准，包括校准存储系统的方法。 该方法包括在存储器件处输入测试模式并测量存储器件上的CWL。 计算CWL和编程CWL之间的差异。 将计算出的差值发送到存储器控制器，该存储器控制器使用计算出的差值来调整定时延迟以匹配所测量的CWL。
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公开(公告)号：US20110199843A1
公开(公告)日：2011-08-18
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US08493801B2
公开(公告)日：2013-07-23
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US20120300564A1
公开(公告)日：2012-11-29
申请号：US13570430
申请日：2012-08-09
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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公开(公告)号：US08284621B2
公开(公告)日：2012-10-09
申请号：US12705674
申请日：2010-02-15
申请人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
发明人： Daniel M. Dreps , Kevin C. Gower , Michael K. Kerr , Kyu-hyoun Kim , David W. Mann , James A. Mossman , Michael A. Sorna , Robert B. Tremaine , William M. Zevin
IPC分类号： G11C8/18
CPC分类号： G06F13/4243 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C2207/2254
摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.
摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。
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8.发明申请公开(公告)号：US20120176850A1
公开(公告)日：2012-07-12
申请号：US12985481
申请日：2011-01-06
申请人： Lydia M. Do , William M. Zevin
发明人： Lydia M. Do , William M. Zevin
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F13/1689 , G11C8/18 , G11C11/406 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.
摘要翻译： 列地址选通写延迟（CWL）校准，包括校准存储系统的方法。 该方法包括在存储器件处输入测试模式并测量存储器件上的CWL。 计算CWL和编程CWL之间的差异。 将计算出的差值发送到存储器控制器，该存储器控制器使用计算出的差值来调整定时延迟以匹配所测量的CWL。
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9.发明授权Method and apparatus for correlating logic analyzer state capture data with associated application data structures 失效用于将逻辑分析仪状态捕获数据与相关联的应用数据结构相关联的方法和装置
公开(公告)号：US5737520A
公开(公告)日：1998-04-07
申请号：US708142
申请日：1996-09-03
CPC分类号： G06F11/322
摘要： Methods and associated apparatus for analyzing and presenting captured state logic data including memory accesses by an intelligent I/O interface device and an attached computer system. The data analysis and display of the present invention aids an engineer in locating data corruption failures in a system. The heuristic analysis of the methods of the present invention locate and identify buffers accessed within the captured state logic data and buffer descriptors accessed within the captured state logic data despite the time dispersion thereof. The buffers and buffer descriptors located and identified within the captured state logic data are displayed on a computer display screen in a manner to more effectively assist an engineer in locating a root cause of data corruption than was possible with prior methods devoid of the analysis of the present invention. In particular, the display visually identifies buffers regardless of the state/time dispersion in the original captured state logic data and distinguishes read access from write access thereto. The display includes indicia used to associate a located and identified buffer descriptor with the identified buffer to which it refers. In response to user requests, the data contained in a selected buffer or selected buffers may be textually displayed either in a raw form or in accordance with the protocol specifications of the underlying data exchange application being debugged. The identified buffers may also be easily searched for a user specified string without concern for the time dispersion of the buffers in the captured state logic data.
摘要翻译： 用于分析和呈现捕获的状态逻辑数据的方法和相关设备，包括由智能I / O接口设备和附接的计算机系统的存储器访问。 本发明的数据分析和显示有助于工程师在系统中定位数据损坏故障。 本发明的方法的启发式分析定位并识别在所捕获的状态逻辑数据和在所捕获状态逻辑数据内访问的缓冲器描述符中访问的缓冲器，尽管其时间分散。 捕获状态逻辑数据中定位和识别的缓冲区和缓冲区描述符以显示在计算机显示屏幕上的方式显示，以更有效地帮助工程师找出数据损坏的根本原因，而不是先前使用的方法， 本发明。 特别地，无论原始捕获状态逻辑数据中的状态/时间分散如何，显示器可视地识别缓冲器，并将读取访问与写入访问区分开。 显示器包括用于将位置和标识的缓冲器描述符与其所指定的所识别的缓冲器相关联的标记。 响应于用户请求，包含在所选择的缓冲器或所选择的缓冲器中的数据可以以原始形式或根据被调试的底层数据交换应用的协议规范进行文本显示。 所识别的缓冲器也可以容易地搜索用户指定的字符串，而不用考虑缓冲器在捕获的状态逻辑数据中的时间分散。
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