公开(公告)号：US5491720A

公开(公告)日：1996-02-13

申请号：US887433

申请日：1992-05-21

申请人： Gordon T. Davis ,  Judith M. Linger ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin ,  Karl-Heinz Ziegenhain

发明人： Gordon T. Davis ,  Judith M. Linger ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin ,  Karl-Heinz Ziegenhain

IPC分类号： H04L25/02 ,  H04L27/00 ,  H04L29/06 ,  H04B1/38

CPC分类号： H04L29/06 ,  H04L25/0262 ,  H04L27/0012 ,  H04L69/18

摘要： A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals. Utilizing the relationship between the response signal and the transmitted sequence of different signals, a data communication device type and transmission speed are determined, and data communications may then be established between the first data communication device and the second data communication device at an optimal transmission speed.

摘要翻译： 一种用于自动确定与数据通信设备类型相关联的数据通信设备类型和传输速度的数据通信系统中的方法和系统。 在传输线上检测到进入通信，并且发送和接收硬件连接到传输线。 接下来，通过传输线从第一数据通信设备发送第一通信协议或第二通信协议中的不同信号的序列。 然后监测传输线路的来自第二数据通信设备的响应信号。 响应于响应于在所发送的不同信号序列内的特定信号的接收，响应信号从第二数据通信设备发起。 利用响应信号和不同信号的发送序列之间的关系，确定数据通信设备类型和传输速度，然后可以以最佳传输速度在第一数据通信设备和第二数据通信设备之间建立数据通信 。

公开(公告)号：US5263054A

公开(公告)日：1993-11-16

申请号：US886674

申请日：1992-05-21

申请人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin

发明人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi ,  William M. Zevin

IPC分类号： H04L25/05 ,  H04L25/38 ,  H04L27/06

CPC分类号： H04L25/05

摘要： An apparatus for efficient computation of a demodulation process on a digital signal processor for a sampled signal, which includes programming a digital signal processor to apply the sampled signal to an interpolating filter to add interpolation samples to the sampled signal, to search the sampled signal for a threshold crossing associated with a start bit, performing a linear interpolation to find a point where the threshold crossing occurs when a threshold crossing is detected, responsive to determining the point of the threshold crossing, determining a center of a start bit when the point of the threshold crossing has been determined, calculating a supplemental delay, and determining center points for subsequent of data bits utilizing the supplemental delay period from the center of the start bit.

摘要翻译： 一种用于对采样信号的数字信号处理器进行解调处理的有效计算的装置，其包括对数字信号处理器进行编程以将采样信号施加到内插滤波器以将采样信号加到采样信号中， 与开始位相关联的阈值交叉，执行线性内插，以在检测到阈值交叉时发现阈值交叉发生的点，响应于确定阈值交叉点，确定起点的中心，当点 已经确定了阈值交叉，计算补充延迟，并且利用来自起始位的中心的补充延迟周期来确定随后的数据位的中心点。

公开(公告)号：US5602848A

公开(公告)日：1997-02-11

申请号：US460951

申请日：1995-06-05

申请人： Lawrence P. Andrews ,  Gordon T. Davis ,  Lee H. House ,  Baiju D. Mandalia ,  Laurence V. Marks ,  William R. Robinson, Jr. ,  John C. Sinibaldi

发明人： Lawrence P. Andrews ,  Gordon T. Davis ,  Lee H. House ,  Baiju D. Mandalia ,  Laurence V. Marks ,  William R. Robinson, Jr. ,  John C. Sinibaldi

IPC分类号： H04Q11/04 ,  H04J3/12

CPC分类号： H04Q11/04 ,  H04Q2213/1305 ,  H04Q2213/13097 ,  H04Q2213/13103 ,  H04Q2213/13213 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/1336

摘要： A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.

摘要翻译： 提供了用于在串行数据端口和数据缓冲器之间进行接口的多模式时分复用（TDM）接口电路。 TDM接口电路包含发射机和接收机部分。 该电路可编程为以各种模式工作，并且能够支持各种多通道TDM接口以及单通道模拟接口。 该电路通过将控制字写入控制寄存器来编程。 在操作中，电路从串行数据端口接口的电路接收帧同步信号，门控位时钟信号和位时钟信号。 输入到基地址寄存器的基地址最多可以提供数据缓冲区地址的最高有效位的9位。 根据控制寄存器中的控制字，使用12位计数器产生数据缓冲器地址的剩余（最低有效位）。

公开(公告)号：US5420888A

公开(公告)日：1995-05-30

申请号：US886676

申请日：1992-05-21

申请人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi

发明人： Gordon T. Davis ,  Baiju D. Mandalia ,  John C. Sinibaldi

IPC分类号： H04L27/152 ,  H04L27/14

CPC分类号： H04L27/1525

摘要： A system and method for efficient operation of a digital signal processor allows execution of a noncoherent FSK demodulation process at the baud rate of the incoming signal. First and second signal detecting channels terminate at a summing junction. A signal sampler for applying a sampled signal to the first and second signal detecting channels. The first and second signal detecting channels each include, in series, a finite impulse response filter for filtering out energy outside a selected bandwidth, automatic gain control and a demodulator. The finite impulse response filter means for the second signal detecting channel further shifts the phase of the sampled signal in the second signal detecting channel approximately 90 degrees relative to the sampled signal in the first signal detecting channel. The demodulator in each signal detecting channel further includes first and second sampled signal transmission paths terminating in a multiplying junction. The first signal transmission path in each demodulator includes a tunable delay line. The decoder takes its input from the summing junction for reproducing a signal indicating presence of a particular frequency or reproduction of the baseband signal.

摘要翻译： 用于数字信号处理器的有效操作的系统和方法允许以输入信号的波特率执行非相干FSK解调过程。 第一和第二信号检测通道终止于加法结。 一种用于将采样信号施加到第一和第二信号检测通道的信号采样器。 第一和第二信号检测通道各自包括用于滤出选定带宽以外的能量的有限脉冲响应滤波器，自动增益控制和解调器。 用于第二信号检测通道的有限脉冲响应滤波器装置进一步使第二信号检测通道中的采样信号的相位相对于第一信号检测通道中的采样信号大约90度。 每个信号检测信道中的解调器还包括终止于乘法结的第一和第二采样信号传输路径。 每个解调器中的第一信号传输路径包括可调延迟线。 解码器从加法结接收其输入，以再现指示特定频率的存在或基带信号的再现的信号。

公开(公告)号：US4991169A

公开(公告)日：1991-02-05

申请号：US227832

申请日：1988-08-02

申请人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

发明人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

IPC分类号： H04M11/06 ,  H04J3/12

CPC分类号： H04J3/12 ,  H04Q2213/13034 ,  H04Q2213/1309 ,  H04Q2213/13103 ,  H04Q2213/13107 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13213 ,  H04Q2213/13215 ,  H04Q2213/13292 ,  H04Q2213/13377 ,  H04Q2213/13396

摘要： A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.).

公开(公告)号：US4871974A

公开(公告)日：1989-10-03

申请号：US289064

申请日：1988-12-23

申请人： Gordon T. Davis ,  Baiju D. Mandalia

发明人： Gordon T. Davis ,  Baiju D. Mandalia

IPC分类号： H04L27/22 ,  H04L27/227

CPC分类号： H04L27/2275

摘要： A demodulator mechanism which uses estimates of the in-phase and quadrature-phase components of differential phase modulated carrier signals for performing a coherent demodulation of these signals is described. The instantaneous estimates, obtained from an estimator circuit, are fed into a differential carrier recovery circuit, which provides for a feedback of ideal sine and cosine components, and combined with the instantaneous estimates for incrementally decreasing a phase error signal generated in a computational circuit. By thus incrementally decreasing the phase error signal, an ideal phase angle is eventually obtained, thereby providing for coherent demodulated output components of the input carrier signals.

公开(公告)号：US5459843A

公开(公告)日：1995-10-17

申请号：US282412

申请日：1994-07-28

申请人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

发明人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3851

摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.

摘要翻译： 以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。 流水线处理器包括指令提取单元，指令解码单元和n个执行单元。 每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令 在一个机器周期内。 定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。

公开(公告)号：US4972342A

公开(公告)日：1990-11-20

申请号：US254985

申请日：1988-10-07

申请人： Gordon T. Davis ,  Baiju D. Mandalia

发明人： Gordon T. Davis ,  Baiju D. Mandalia

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F9/3885 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/3804

摘要： A special purpose circuit unit, responsive to a special BBD instruction, provides for more efficient execution of program branches required in poll and test type routines used by data processors. This unit can easily be added to almost any contemporary processing system to speed up performance of priority branch operations. It includes: a stack of registers loadable with branch addresses designating locations of branch target instructions, an input register for holding bits representing branch conditions accessible from immediate (programmable) storage, and a programmable priority encoder responsive to the BBD instruction to select an address from the stack in accordance with the position in the input register of a highest priority one of the bits representing an active request for instruction branching. The selected address is used to fetch an instruction representing the start of a program segment for attending to the selected branch condition. Contents of the branch address stack are alterable by program to allow for varying selections of branch routines to fulfill conditions denotable by different sets of bits loadable into the input register. The priority encoder includes a stack of selection control registers which are also loadable by programs, to allow for variability in the priority ordering accorded to the bit positions of the input register. By dynamically loading information into the branch address and priority selection stacks, subject BBD unit can be shared dynamically for resolving sequence branching relative to multiple different classes of conditions or events depending on system requirements. The unit is configurable to execute its priority and branch address selection operations together in a single clock cycle of the system. In pipelined systems, the BBD function can be conveniently accommodated in parallel with other system functions.

公开(公告)号：US4991133A

公开(公告)日：1991-02-05

申请号：US254986

申请日：1988-10-07

申请人： Gordon T. Davis ,  Robert E. Landa ,  Baiju D. Mandalia ,  Jan W. van den Berg ,  David C. Van Voorhis

发明人： Gordon T. Davis ,  Robert E. Landa ,  Baiju D. Mandalia ,  Jan W. van den Berg ,  David C. Van Voorhis

IPC分类号： G06F13/00 ,  G06F13/12 ,  H04L29/06 ,  H04L29/10

CPC分类号： G06F13/128 ,  H04L29/06 ,  H04L69/12

摘要： A special purpose communications protocol processor (CPP) provides more efficient processing of layered communications protocols--e.g. SNA (Systems Network Architecture) and OSI (Open Systems Interconnection)--than contemporary general purpose processors, permitting hitherto unavailable operations relative to high speed communication links. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, such functions and information being of the sort repeatedly encountered in all protocol layers, and uses instructions architected to operate these circuits. The header processing functions given special treatment in this manner include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions. Frame processing functions so handled include CRC (cyclic redundancy check) computations, bit insertion/deletion operations and special character detection operations.

公开(公告)号：US4899366A

公开(公告)日：1990-02-06

申请号：US227582

申请日：1988-08-02

申请人： Gordon T. Davis ,  Baiju D. Mandalia

发明人： Gordon T. Davis ,  Baiju D. Mandalia

IPC分类号： H04B3/04 ,  H04L7/02

CPC分类号： H04L7/0058

摘要： In a modem receiver having a fixed sample rate relative to incoming symbols and a tapped delay adaptive equalizer with fractional tap spacing, coefficients used in the equalization computations are rotated relative to a reference tap in order to compensate for relative drift between incoming signals, representing real (i.e. non-training) data, and the clock controlling sampling. By itself, such rotation would tend to distort received data by shifting the sampling phase away from the center of the received symbols. Logic means included herewith operates to prevent such distortion, so that the integrity of the data output of the receiver is unaffected by the rotation. In the disclosed embodiment, such logic means operates to shift the phase of the "sum of products" computation (product of data and tap coefficients) relative to the flow of data into the fractionally spaced delay network. Since the present receiver does not require synchronization with incoming symbols it is well adapted to function in environments where such synchronization would be difficult to provide; for example, in situations where data transmitted at various baud rates is received via a digital carrier trunk and requires equalization or comparable filter processing.