公开(公告)号：US4991169A

公开(公告)日：1991-02-05

申请号：US227832

申请日：1988-08-02

申请人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

发明人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

IPC分类号： H04M11/06 ,  H04J3/12

CPC分类号： H04J3/12 ,  H04Q2213/13034 ,  H04Q2213/1309 ,  H04Q2213/13103 ,  H04Q2213/13107 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13213 ,  H04Q2213/13215 ,  H04Q2213/13292 ,  H04Q2213/13377 ,  H04Q2213/13396

摘要： A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.).

公开(公告)号：US5602848A

公开(公告)日：1997-02-11

申请号：US460951

申请日：1995-06-05

申请人： Lawrence P. Andrews ,  Gordon T. Davis ,  Lee H. House ,  Baiju D. Mandalia ,  Laurence V. Marks ,  William R. Robinson, Jr. ,  John C. Sinibaldi

发明人： Lawrence P. Andrews ,  Gordon T. Davis ,  Lee H. House ,  Baiju D. Mandalia ,  Laurence V. Marks ,  William R. Robinson, Jr. ,  John C. Sinibaldi

IPC分类号： H04Q11/04 ,  H04J3/12

CPC分类号： H04Q11/04 ,  H04Q2213/1305 ,  H04Q2213/13097 ,  H04Q2213/13103 ,  H04Q2213/13213 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/1336

摘要： A multi-mode time division multiplexing (TDM) interface circuit for interfacing between a serial data port and a data buffer is provided. The TDM interface circuit contains a transmitter and a receiver section. The circuit is programmable to operate in a variety of modes and is capable of supporting various multi-channel TDM interfaces as well as single channel analog interfaces. The circuit is programmable by writing a control word to a control register. In operation the circuit receives a frame synchronization signal, a gated bit clock signal, and a bit clock signal from the circuit with which it is interfacing on the serial data port. A base address input to a base address register provides up to 9 of the most significant bits of a data buffer address. A 12-bit counter is used to generate the remaining (least significant) bits of the data buffer address according to the control word in the control register.

摘要翻译： 提供了用于在串行数据端口和数据缓冲器之间进行接口的多模式时分复用（TDM）接口电路。 TDM接口电路包含发射机和接收机部分。 该电路可编程为以各种模式工作，并且能够支持各种多通道TDM接口以及单通道模拟接口。 该电路通过将控制字写入控制寄存器来编程。 在操作中，电路从串行数据端口接口的电路接收帧同步信号，门控位时钟信号和位时钟信号。 输入到基地址寄存器的基地址最多可以提供数据缓冲区地址的最高有效位的9位。 根据控制寄存器中的控制字，使用12位计数器产生数据缓冲器地址的剩余（最低有效位）。

公开(公告)号：US5459843A

公开(公告)日：1995-10-17

申请号：US282412

申请日：1994-07-28

申请人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

发明人： Gordon T. Davis ,  Sebastian T. Ventrone ,  John J. Reilly ,  Baiju D. Mandalia ,  Michael G. Holung ,  William R. Robinson, Jr.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3851

摘要： A pipelined, RISC-type processor operated in parallel mode and its associated processing methods for separately handling instructions from multiple program instruction sets. The pipelined processor includes an instruction fetch unit, an instruction decode unit and n execution units. Each execution unit operates at substantially the same process cycle time, while the speed of operation of the instruction fetch unit and instruction decode unit is at least n times the cycle time of the execution units such that each phase of the pipeline separately processes n instructions substantially within one machine cycle. Timing and control circuitry is coupled to each of the principle elemental units for controlling the timing and sequence of operations on instructions.

摘要翻译： 以并行模式运行的流水线RISC型处理器及其相关处理方法，用于分别处理来自多个程序指令集的指令。 流水线处理器包括指令提取单元，指令解码单元和n个执行单元。 每个执行单元以基本上相同的处理周期时间操作，而指令获取单元和指令解码单元的操作速度至少为执行单元的周期时间的n倍，使得流水线的每个相分别基本上处理n个指令 在一个机器周期内。 定时和控制电路耦合到每个主要元件单元，用于控制指令上的操作的时序和顺序。