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    Process for manufacturing metal-semiconductor field-effect transistors
    4.
    发明授权
    Process for manufacturing metal-semiconductor field-effect transistors 失效
    制造金属半导体场效应晶体管的工艺

    公开(公告)号：US4731339A

    公开(公告)日：1988-03-15

    申请号：US899574

    申请日：1986-08-25

    申请人： Frank J. Ryan ,  Man-Chung F. Chang ,  Dennis A. Williams ,  Richard P. Vahrenkamp

    发明人： Frank J. Ryan ,  Man-Chung F. Chang ,  Dennis A. Williams ,  Richard P. Vahrenkamp

    IPC分类号： H01L21/338 ,  B44C1/22

    CPC分类号： H01L29/66871

    摘要： A single-level photoresist process is used to make metal-semiconductor field-effect transistors (MESFETs) having more uniform threshold voltages. An N.sup.- layer is formed in a semi-insulating semiconductor, followed by formation of a dummy gate using a single-level photoresist process. Using the dummy gate as a mask, ions are implanted to form an N.sup.+ region. The length of the dummy gate is then reduced by plasma etching. A dielectric is deposited over the N.sup.+ region, the N.sup.+ /N.sup.- interface, and the exposed portion of the N.sup.- layer. The dummy gate is lifted off to define a self-aligned, submicron gate opening. The gate opening on the N.sup.- layer is reactive ion etched to obtain the desired threshold voltage, and covered with a Schottky gate metal deposit.

    摘要翻译： 使用单级光刻胶工艺来制造具有更均匀阈值电压的金属半导体场效应晶体管（MESFET）。 在半绝缘半导体中形成N-层，然后使用单层光致抗蚀剂工艺形成虚拟栅极。 使用伪栅极作为掩模，注入离子以形成N +区域。 然后通过等离子体蚀刻减少虚拟栅极的长度。 电介质沉积在N +区域上，N + / N-界面和N层的暴露部分。 虚拟门被提起以限定自对准的亚微米门开口。 N-层上的栅极开口被反应离子蚀刻以获得所需的阈值电压，并用肖特基栅极金属沉积物覆盖。

    Three metal personalization of application specific monolithic microwave integrated circuit
    7.
    发明授权
    Three metal personalization of application specific monolithic microwave integrated circuit 失效
    应用特定单片微波集成电路的三金属个性化

    公开(公告)号：US5162258A

    公开(公告)日：1992-11-10

    申请号：US496399

    申请日：1990-03-20

    申请人： Zachary J. Lemnios ,  David G. McIntyre ,  Chung-Lim Lau ,  Dennis A. Williams

    发明人： Zachary J. Lemnios ,  David G. McIntyre ,  Chung-Lim Lau ,  Dennis A. Williams

    IPC分类号： H01L27/06 ,  H01L27/118

    CPC分类号： H01L27/118 ,  H01L27/0605

    摘要： A (GaAs-resident) application specific monolithic microwave integrated circuit (ASMMIC) is fabricated through the use of footprints that include a portion of the metallization through which the circuit components within the wafer are to be interconnected. The metallization is a three layers structure, the first two layers of which include strategically arranged reactance circuit components (MIM) capacitors. A first of the three metal layers is formed on a first surface of the substrate which contains a plurality of semiconductor device regions and conductive material for ohmic contact to the regions, so that portions of the first metal layer are in ohmic contact with the conductive material. The first metal layer provides the bottom plate of the MIM capacitors. A dielectric layer, which serves as the dielectric insulator of the MIM capacitors, is formed on second portions of the first metal layer. A second, intermediate metal layer is selectively formed on the second portions of the first metal layer, to provide top plate segments of MIM capacitors. Personalization of the footprint is effected by an air bridge metal layer interconnecting the first and second metal layers and thereby semiconductor device regions of the semiconductor structure with capacitive reactance elements formed by the first and second metal layers.

    摘要翻译： 通过使用包括金属化部分的覆盖区域来制造（GaAs驻留）专用单片微波集成电路（ASMMIC），其中晶片内的电路部件通过该部分互连。 金属化是三层结构，其前两层包括策略布置的电抗电路元件（MIM）电容器。 三个金属层中的第一个形成在基板的第一表面上，该第一表面包含多个半导体器件区域和用于与区域欧姆接触的导电材料，使得第一金属层的部分与导电材料欧姆接触 。 第一金属层提供MIM电容器的底板。 用作MIM电容器的电介质绝缘体的电介质层形成在第一金属层的第二部分上。 在第一金属层的第二部分选择性地形成第二中间金属层，以提供MIM电容器的顶板段。 通过由第一和第二金属层互连的空气桥金属层和由半导体结构的半导体器件区域与由第一和第二金属层形成的电容性电抗元件互连来实现覆盖区的个性化。