公开(公告)号：US07543132B1

公开(公告)日：2009-06-02

申请号：US10880985

申请日：2004-06-30

申请人： Greg F. Grohoski ,  Ashley Saulsbury ,  Paul J. Jordan ,  Manish Shah ,  Rabin A. Sugumar ,  Mark Debbage ,  Venkatesh Iyengar

发明人： Greg F. Grohoski ,  Ashley Saulsbury ,  Paul J. Jordan ,  Manish Shah ,  Rabin A. Sugumar ,  Mark Debbage ,  Venkatesh Iyengar

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/0817 ,  G06F12/0897 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/684

摘要： A method and apparatus for improved performance for reloading translation look-aside buffers in multithreading, multi-core processors. TSB prediction is accomplished by hashing a plurality of data parameters and generating an index that is provided as an input to a predictor array to predict the TSB page size. In one embodiment of the invention, the predictor array comprises two-bit saturating up-down counters that are used to enhance the accuracy of the TSB prediction. The saturating up-down counters are configured to avoid making rapid changes in the TSB prediction upon detection of an error. Multiple misses occur before the prediction output is changed. The page size specified by the predictor index is searched first. Using the technique described herein, errors are minimized because the counter leads to the correct result at least half the time.

摘要翻译： 一种用于在多线程，多核处理器中重新加载翻译后备缓冲器的性能的方法和装置。 通过散列多个数据参数并生成作为预测器阵列的输入提供的索引来预测TSB页面大小来实现TSB预测。 在本发明的一个实施例中，预测器阵列包括用于增强TSB预测精度的二位饱和上拉计数器。 饱和上拉计数器配置为避免在检测到错误时对TSB预测进行快速更改。 在预测输出改变之前会发生多重错误。 首先搜索由预测变量索引指定的页面大小。 使用本文描述的技术，误差被最小化，因为计数器至少在一半的时间内导致正确的结果。

公开(公告)号：US07290116B1

公开(公告)日：2007-10-30

申请号：US10881714

申请日：2004-06-30

申请人： Greg F. Grohoski ,  Manish Shah ,  John D. Davis ,  Ashley Saulsbury ,  Cong Fu ,  Venkatesh Iyengar ,  Jenn-Yuan Tsai ,  Jeff Gibson

发明人： Greg F. Grohoski ,  Manish Shah ,  John D. Davis ,  Ashley Saulsbury ,  Cong Fu ,  Venkatesh Iyengar ,  Jenn-Yuan Tsai ,  Jeff Gibson

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0864

摘要： An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.

摘要翻译： 结合多线程多处理器芯片描述了用于映射存储器地址以减少或避免诸如高速缓冲存储器的存储器系统中的冲突存储器访问的装置和方法。 CMT处理器通过对物理缓存地址的某些位进行散列来形成一个散列缓存地址来降低高速缓存操作中热点的概率。 通过使用异或功能对索引位进行散列，实现了高效的地址转换，用于索引到L2高速缓存中。

公开(公告)号：US07996632B1

公开(公告)日：2011-08-09

申请号：US11615914

申请日：2006-12-22

申请人： Greg F. Grohoski ,  Mark A. Luttrell ,  Manish Shah

发明人： Greg F. Grohoski ,  Mark A. Luttrell ,  Manish Shah

IPC分类号： G06F12/00

CPC分类号： G06F9/3004 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/34 ,  G06F9/3824 ,  G06F12/0846

摘要： A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is aligned. The core executing the instruction determines whether the atomic memory address source data is aligned. If it is aligned, the atomic memory address is sent to the bank that contains the atomic memory address source data, and the operation is executed in the bank. In one embodiment, if the instruction is mis-aligned, the operation is executed in the core.

摘要翻译： 提供了具有存储缓存的多线程处理器。 如果原子存储器地址源数据对齐，则指令集包括在L2高速缓存中执行的至少一个原子操作。 执行指令的核心决定原子存储器地址源数据是否对齐。 如果对齐，则原子存储器地址被发送到包含原子存储器地址源数据的存储体，并且该操作在存储体中执行。 在一个实施例中，如果指令错误对准，则在核心中执行操作。