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1.发明申请Write-Through-Read (WTR) Comparator Circuits, Systems, and Methods Employing Write-Back Stage and Use of Same With A Multiple-Port File 有权直写读取（WTR）比较器电路，系统和采用回写阶段的方法和使用与多端口文件相同公开(公告)号：US20110197021A1
公开(公告)日：2011-08-11
申请号：US12703342
申请日：2010-02-10
申请人： Gregory Christopher Burda , Michael Scott McIlvaine , Nathan Samuel Nunamaker , Yeshwant Nagaraj Kolla
发明人： Gregory Christopher Burda , Michael Scott McIlvaine , Nathan Samuel Nunamaker , Yeshwant Nagaraj Kolla
IPC分类号： G06F12/00
CPC分类号： G06F9/30141 , G06F9/3857
摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.
摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。
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2.发明授权Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port file 有权直写读取（WTR）比较器电路，系统和采用回写阶段的方法以及使用多端口文件公开(公告)号：US08578117B2
公开(公告)日：2013-11-05
申请号：US12703342
申请日：2010-02-10
申请人： Gregory Christopher Burda , Michael Scott McIlvaine , Nathan Samuel Nunamker , Yeshwant Nagaraj Kolla
发明人： Gregory Christopher Burda , Michael Scott McIlvaine , Nathan Samuel Nunamker , Yeshwant Nagaraj Kolla
IPC分类号： G06F12/00
CPC分类号： G06F9/30141 , G06F9/3857
摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.
摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。
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3.发明申请Power Saving Static-Based Comparator Circuits and Methods and Content-Addressable Memory (CAM) Circuits Employing Same 有权基于省电静态比较器电路和方法以及内容寻址存储器（CAM）采用相同的电路公开(公告)号：US20100182816A1
公开(公告)日：2010-07-22
申请号：US12357767
申请日：2009-01-22
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F17/30982 , Y02D10/45
摘要： Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.
摘要翻译： 公开了基于静态的比较器和用于比较数据的方法。 基于静态的比较器被配置为响应于对比数据与比较数据的比较以及数据的有效性指示符来选择性地切换至少一个比较器输出。 如果有效性指示符指示有效数据，则基于静态的比较器切换以驱动比较器输出，指示相应比较数据之间的匹配或不匹配。 如果有效性指示符指示无效数据，则基于静态的比较器会提供比较器输出的不匹配，而不用切换基于静态的比较器，而不管数据是否与比较数据匹配。 以这种方式，基于静态的比较器不会消耗电源切换比较器输出，标记为无效数据。 基于静态的比较器可以用于内容可寻址存储器（CAM）中，用于将标签数据的一个或多个比特与比较数据的相应比特进行比较。
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4.发明授权Power saving static-based comparator circuits and methods and content-addressable memory (CAM) circuits employing same 有权基于省电静态的比较器电路和方法以及采用该方法的内容寻址存储器（CAM）电路公开(公告)号：US08315078B2
公开(公告)日：2012-11-20
申请号：US12357767
申请日：2009-01-22
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G06F17/30982 , Y02D10/45
摘要： Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data.
摘要翻译： 公开了基于静态的比较器和用于比较数据的方法。 基于静态的比较器被配置为响应于对比数据与比较数据的比较以及数据的有效性指示符来选择性地切换至少一个比较器输出。 如果有效性指示符指示有效数据，则基于静态的比较器切换以驱动比较器输出，指示相应比较数据之间的匹配或不匹配。 如果有效性指示符指示无效数据，则基于静态的比较器会提供比较器输出的不匹配，而不用切换基于静态的比较器，而不管数据是否与比较数据匹配。 以这种方式，基于静态的比较器不会消耗电源切换比较器输出，标记为无效数据。 基于静态的比较器可以用于内容可寻址存储器（CAM）中，用于将标签数据的一个或多个比特与比较数据的相应比特进行比较。
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5.发明申请Bi-Modal Power Delivery Scheme for Integrated Circuits that Enables Fine Grain Power Management for Multiple Functional Blocks on a Single Die 有权用于集成电路的双模态电力输送方案，可在单个芯片上实现多个功能块的细粒度电源管理公开(公告)号：US20130332748A1
公开(公告)日：2013-12-12
申请号：US13489859
申请日：2012-06-06
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3203 , Y02D10/124
摘要： Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.
摘要翻译： 用于向包括功能块的集成电路提供双模态和细粒度功率的系统和方法。 第一电源耦合到集成电路的功能块，用于支持功能块的第一操作模式。 第二电源耦合到功能块，用于支持功能块的第二操作模式。 第一和第二种工作模式可分别为高频和低频模式。 第二电源可以使用片上稳压器或独立提供的来自第一电源。 可以通过控制第一和第二电源的占空比来实现功能块的期望平均吞吐量。
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6.发明授权Bi-modal power delivery scheme for an integrated circuit comprising multiple functional blocks on a single die to achieve desired average throughput for the integrated circuit 有权一种用于集成电路的双模式功率输送方案，其包括在单个管芯上的多个功能块，以实现集成电路的期望的平均吞吐量公开(公告)号：US09134777B2
公开(公告)日：2015-09-15
申请号：US13489859
申请日：2012-06-06
CPC分类号： G06F1/26 , G06F1/32 , G06F1/3203 , Y02D10/124
摘要： Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.
摘要翻译： 用于向包括功能块的集成电路提供双模态和细粒度功率的系统和方法。 第一电源耦合到集成电路的功能块，用于支持功能块的第一操作模式。 第二电源耦合到功能块，用于支持功能块的第二操作模式。 第一和第二种工作模式可分别为高频和低频模式。 第二电源可以使用片上稳压器或独立提供的来自第一电源。 可以通过控制第一和第二电源的占空比来实现功能块的期望平均吞吐量。
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