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    Write-Through-Read (WTR) Comparator Circuits, Systems, and Methods Employing Write-Back Stage and Use of Same With A Multiple-Port File
    1.
    发明申请
    Write-Through-Read (WTR) Comparator Circuits, Systems, and Methods Employing Write-Back Stage and Use of Same With A Multiple-Port File 有权
    直写读取（WTR）比较器电路，系统和采用回写阶段的方法和使用与多端口文件相同

    公开(公告)号：US20110197021A1

    公开(公告)日：2011-08-11

    申请号：US12703342

    申请日：2010-02-10

    申请人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamaker ,  Yeshwant Nagaraj Kolla

    发明人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamaker ,  Yeshwant Nagaraj Kolla

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30141 ,  G06F9/3857

    摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

    摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。

    Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port file
    2.
    发明授权
    Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port file 有权
    直写读取（WTR）比较器电路，系统和采用回写阶段的方法以及使用多端口文件

    公开(公告)号：US08578117B2

    公开(公告)日：2013-11-05

    申请号：US12703342

    申请日：2010-02-10

    申请人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamker ,  Yeshwant Nagaraj Kolla

    发明人： Gregory Christopher Burda ,  Michael Scott McIlvaine ,  Nathan Samuel Nunamker ,  Yeshwant Nagaraj Kolla

    IPC分类号： G06F12/00

    CPC分类号： G06F9/30141 ,  G06F9/3857

    摘要： Write-through-read (WTR) comparator circuits and related WTR processes and memory systems are disclosed. The WTR comparator circuits can be configured to perform WTR functions for a multiple port file having one or more read and write ports. One or more WTR comparators in the WTR comparator circuit are configured to compare a read index into a file with a write index corresponding to a write-back stage selected write port among a plurality of write ports that can write data to the entry in the file. The WTR comparators then generate a WTR comparator output indicating whether the write index matches the read index to control a WTR function. In this manner, the WTR comparator circuit can employ less WTR comparators than the number of read and write port combinations. Providing less WTR comparators can reduce power consumption, cost, and area required on a semiconductor die for the WTR comparator circuit.

    摘要翻译： 通读（WTR）比较器电路和相关的WTR处理和存储器系统被公开。 WTR比较器电路可以被配置为对具有一个或多个读取和写入端口的多端口文件执行WTR功能。 WTR比较器电路中的一个或多个WTR比较器被配置为将读取的索引与可以将数据写入文件中的条目的多个写入端口中的读取索引与对应于写回阶段选择的写入端口的写入索引进行比较 。 WTR比较器然后产生WTR比较器输出，指示写入索引是否与读取索引匹配以控制WTR功能。 以这种方式，WTR比较器电路可以使用比读取和写入端口组合数更少的WTR比较器。 提供较少的WTR比较器可以降低用于WTR比较器电路的半导体管芯所需的功耗，成本和面积。

    Segmented Pipeline Flushing for Mispredicted Branches
    8.
    发明申请
    Segmented Pipeline Flushing for Mispredicted Branches 有权
    分段管道冲洗用于预测分支

    公开(公告)号：US20080177992A1

    公开(公告)日：2008-07-24

    申请号：US11626443

    申请日：2007-01-24

    申请人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    发明人： Rodney Wayne Smith ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

    IPC分类号： G06F9/38

    CPC分类号： G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3867

    摘要： A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.

    摘要翻译： 处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。 在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。 较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。 可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

    Power efficient instruction prefetch mechanism
    9.
    发明授权
    Power efficient instruction prefetch mechanism 有权
    高效的指令预取机制

    公开(公告)号：US08661229B2

    公开(公告)日：2014-02-25

    申请号：US12434804

    申请日：2009-05-04

    申请人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    发明人： Thomas Andrew Sartorius ,  Victor Roberts Augsburg ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Rodney Wayne Smith

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

    CPC分类号： G06F9/3844 ,  G06F9/3804

    摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.

    摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。