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1.发明授权Circuitry for providing external access to signals that are internal to an integrated circuit chip package 失效用于提供对集成电路芯片封装内部信号的外部访问的电路
公开(公告)号：US6003107A
公开(公告)日：1999-12-14
申请号：US707936
申请日：1996-09-10
CPC分类号： G06F7/02
摘要： Circuitry for providing external access to signals that are internal to an integrated circuit chip package. A plurality of N:1 multiplexers are physically distributed throughout the integrated circuit die. Each of the multiplexers has its N inputs coupled to a nearby set of N nodes within the integrated circuit, and each of the multiplexers is coupled to a source of select information operable to select one node from the set of N nodes for external access. Each of the multiplexers has its output coupled to an externally-accessible chip pad. The integrated circuit is a microprocessor, and the source of select information may include a storage element. If so, additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions. Each multiplexer may be coupled to a different source of select information, or all multiplexers may be coupled to the same select information. Moreover, a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally-accessible chip pads. One or more M:1 multiplexers may also be provided, having their M inputs coupled to M different outputs of the N:1 multiplexers. Each of the M:1 multiplexers may be coupled to a second source of select information. Preferably, the outputs of the M:1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit.
摘要翻译： 用于提供对集成电路芯片封装内部信号的外部访问的电路。 多个N：1复用器物理地分布在整个集成电路管芯中。 每个复用器具有其N个输入耦合到集成电路内的附近的一组N个节点，并且每个多路复用器耦合到可选择信息的源，用于从用于外部访问的N个节点的集合中选择一个节点。 每个多路复用器的输出耦合到外部可访问的芯片焊盘。 集成电路是微处理器，选择信息的源可以包括存储元件。 如果是这样，则提供附加电路用于使用一个或多个微处理器指令将数据从微处理器的寄存器写入存储元件。 每个复用器可以耦合到不同的选择信息源，或者所有复用器可以耦合到相同的选择信息。 此外，可以提供固定的一组互连轨迹以将固定的一组节点耦合到另外一组外部可访问的芯片焊盘。 还可以提供一个或多个M：1多路复用器，其M个输入端耦合到N：1多路复用器的M个不同输出。 M：1多路复用器中的每一个可以耦合到第二选择信息源。 优选地，M：1多路复用器的输出将耦合到用于促进集成电路的调试和性能监视的电路。
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2.发明授权
公开(公告)号：US5880671A
公开(公告)日：1999-03-09
申请号：US742193
申请日：1996-10-31
CPC分类号： G06F11/364 , G06F11/3648 , G06F7/02
摘要： Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output.One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden. The first and second comparison outputs may be generated by bit-wise comparing first and second portions of the bus with first and second expected signal patterns. The logical AND of the respective comparison results may be treated as the first and second comparison outputs, or they may be treated as first and second intermediate bits. These first and second intermediate bits may be ORed with first and second mask bits, and the results may be treated as the first and second comparison outputs. The outputs of the two OR operations may also be EXCLUSIVE ORed with first and second negate bits, respectively.
摘要翻译： 用于检测多位总线上的信号模式的电路。 第一比较电路监视总线的第一部分，将其与第一预期信号模式相比较，产生第一比较输出。 第二比较电路监视总线的第二部分，将其与第二预期信号模式相比较，产生第二比较输出。 两个比较输出都施加到与门和第一或门。 多路复用器的一个数据输入耦合到第一或门的输出。 另一个数据输入耦合到与门的输出。 另一数据输入耦合到第一比较输出，另一数据输入耦合到第二比较输出。 第二或门的一个输入可以耦合到多路复用器输出，另一个输入耦合到禁用指示符，允许多路复用器输出被覆盖。 第一和第二比较输出可以通过比较第一和第二预期信号模式来比较总线的第一和第二部分来产生。 各个比较结果的逻辑“与”可被视为第一和第二比较输出，或者它们可被视为第一和第二中间位。 这些第一和第二中间位可以与第一和第二屏蔽位进行“或”运算，并且结果可被视为第一和第二比较输出。 两个OR运算的输出也可以分别与第一和第二否定位独占或。
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3.发明授权Apparatus and method for reading and writing remote registers on an integrated circuit chip using a minimum of interconnects 失效使用最少的互连在集成电路芯片上读写远程寄存器的装置和方法
公开(公告)号：US5644609A
公开(公告)日：1997-07-01
申请号：US690466
申请日：1996-07-31
IPC分类号： G01R31/3185 , G11C19/00
CPC分类号： G01R31/318558 , G11C19/00
摘要： A method and apparatus is disclosed for reading data from and writing data to remote registers that are dispersed throughout an integrated circuit chip. Regardless of the size or number of remote registers involved, the operation is accomplished using only two interconnect lines, plus a clock. Each remote register is associated with a unique address. During a write operation, a microprocessor loads the write data into a staging register, loads the destination address into a header generation register along with a read/write control bit, and loads a count value into a clock. Thereafter, the apparatus of the invention proceeds automatically, as the clock counts down, to shift the data onto a serial data line following a header. Each of the remote registers in the system are arranged serially, and each monitors the header information, comparing the address contained in the header with its own address. In the event of a match, the remote register selected is enabled to shift data serially into itself from the serial data line. During a read operation, the selected remote register shifts its data out onto the serial data line. The read data is ultimately shifted back into the staging register.
摘要翻译： 公开了一种用于从分散在整个集成电路芯片中的远程寄存器读取数据并向其写入数据的方法和装置。 无论涉及的远程寄存器的大小或数量如何，仅使用两条互连线加上一个时钟来完成此操作。 每个远程寄存器与唯一地址相关联。 在写入操作期间，微处理器将写入数据加载到暂存寄存器中，将目标地址与读/写控制位一起加载到标题生成寄存器中，并将计数值加载到时钟中。 此后，本发明的装置随着时钟倒计时自动进行，以将数据移动到标题之后的串行数据线上。 系统中的每个远程寄存器被串行地排列，并且每个监视头信息，将标题中包含的地址与其自己的地址进行比较。 在匹配的情况下，所选的远程寄存器被使能以使数据从串行数据线连续地自动转移。 在读操作期间，所选的远程寄存器将其数据移出到串行数据线上。 读取的数据最终被转移回登录寄存器。
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4.发明授权System and method for on-chip debug support and performance monitoring in a microprocessor 失效用于微处理器中片上调试支持和性能监控的系统和方法
公开(公告)号：US5867644A
公开(公告)日：1999-02-02
申请号：US711491
申请日：1996-09-10
申请人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Russell C. Brockmann , Robert E. Naas , Jonathan P. Lotz , Douglas B. Hunt , Patrick Knebel , Paul L. Perez , Steven T. Mangelsdorf
发明人： Gregory L. Ranson , John W. Bockhaus , Gregg B. Lesartre , Russell C. Brockmann , Robert E. Naas , Jonathan P. Lotz , Douglas B. Hunt , Patrick Knebel , Paul L. Perez , Steven T. Mangelsdorf
CPC分类号： G06F11/3648 , G06F11/364
摘要： User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.
摘要翻译： 用户可配置的诊断硬件包含微处理器，用于调试和监视微处理器的性能。 使用方法 可编程状态机耦合到片上和片外输入源。 状态机可以被编程为寻找由输入源呈现的信号模式，并且通过将某些控制信息驱动到状态机输出总线上来响应定义的模式（或定义的模式的序列）的出现。 耦合到输出总线的片上设备采用由总线指示的用户可定义的动作。 输入源包括位于微处理器的功能块内的用户可配置比较器。 比较器耦合到微处理器内的存储元件，并且被配置为监视节点以确定节点的状态是否与包含在存储元件中的数据匹配。 通过改变存储元件中的数据，程序员可以改变比较节点状态的信息，以及进行比较的方法。 输出设备包括计数器。 计数器输出可以用作状态机输入，因此可以将一个事件定义为发生一定次数的不同事件的功能。 输出设备还包括用于产生内部和外部触发的电路。 用户可配置的多路复用器电路可以用于将用户可选择的信号从微处理器传送到芯片的输出焊盘，并且选择要用作状态机输入的各种内部信号。
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5.发明授权Apparatus and method for tracking events in a microprocessor that can retire more than one instruction during a clock cycle 失效用于跟踪微处理器中的事件的装置和方法，其可以在时钟周期期间退出多于一个指令
公开(公告)号：US5881224A
公开(公告)日：1999-03-09
申请号：US711574
申请日：1996-09-10
CPC分类号： G06F9/3865 , G06F11/076 , G06F11/2236 , G06F11/348 , G06F9/30032 , G06F9/30101 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F11/3409 , G06F2201/88
摘要： In one embodiment, the invention includes a method of tracking events in a microprocessor that can retire more than one instruction during a clock cycle. A set of match results is generated during each clock cycle, one match result for each retiring instruction. Each of the match results indicates whether the corresponding retiring instruction matched a criterion. Then, the total number of retiring instruction that matched the criterion is determined by adding the asserted match results to generate a sum. A counter is incremented by the sum. In another embodiment, the invention includes circuitry for implementing the just-described method. Match generator circuitry is provided for generating a set of match results during each clock cycle, one match result for each retiring instruction. The outputs of the match generator circuitry are supplied to adder circuitry. The adder circuitry is operable to determine the number of said match results that are asserted and to represent the number as a sum via a set of adder circuitry outputs. A counter having a set of adder circuitry inputs is coupled to adder circuitry outputs. The counter is operable to increment its count by the sum represented by the adder circuitry outputs. In further embodiments, a multiplexer is interposed between the adder circuitry and the counter. The multiplexer has a first set of inputs coupled to the adder circuitry outputs, and a second set of inputs coupled to a source of the value "1." The multiplexer is operable to present either the first or second inputs on its outputs responsive to a select signal. The multiplexer has its outputs coupled to the increment inputs of the counter.
摘要翻译： 在一个实施例中，本发明包括跟踪微处理器中的事件的方法，其可以在时钟周期期间退出多于一个指令。 在每个时钟周期内产生一组匹配结果，每个退出指令一个匹配结果。 每个匹配结果指示相应的退出指令是否匹配标准。 然后，通过添加所断言的匹配结果以产生和来确定与标准匹配的退休指令的总数。 一个计数器增加一个和。 在另一个实施例中，本发明包括用于实现刚刚描述的方法的电路。 匹配发生器电路被提供用于在每个时钟周期期间产生一组匹配结果，每个退出指令的一个匹配结果。 匹配发生器电路的输出被提供给加法器电路。 加法器电路可操作以确定所确定的所述匹配结果的数量，并且经由一组加法器电路输出将数字表示为和。 具有一组加法器电路输入的计数器耦合到加法器电路输出。 计数器可操作地将其计数增加由加法器电路输出表示的和。 在另外的实施例中，多路复用器插在加法器电路和计数器之间。 多路复用器具有耦合到加法器电路输出的第一组输入和耦合到值“1”的源的第二组输入。 多路复用器可操作以响应于选择信号在其输出上呈现第一或第二输入。 多路复用器的输出端与计数器的增量输入相连。
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6.发明授权Circuitry and method for detecting signal patterns on a bus using dynamically changing expected patterns 失效使用动态变化的预期模式来检测总线上的信号模式的电路和方法
公开(公告)号：US5956476A
公开(公告)日：1999-09-21
申请号：US741563
申请日：1996-10-31
CPC分类号： G06F11/1443
摘要： Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus. First storage circuitry stores a record of the first detection signal having been asserted. Second storage circuitry stores the transaction identifying indicia present on the bus when the first signal pattern is detected. Second comparison circuitry compares the signal patterns on the bus with a stored signal pattern, and third comparison circuitry compares the transaction identifying indicia present on the bus with the indicia stored in the second storage circuitry. When the second and third comparison circuitries simultaneously indicate matches and the first storage circuitry indicates that the first signal pattern was previously detected, output generation circuitry asserts a match signal.
摘要翻译： 用于检测在具有事务识别标记的分割事务总线上何时发生第一和第二信号模式的方法：将总线上发生的信号模式与第一存储的信号模式进行比较。 如果检测到匹配，则存储与总线上与第一信号模式相关联的交易识别标记，并且第一检测信号被断言并保持断言。 然后将总线上的信号模式与第二存储的信号模式进行比较，并将总线上发生的事务识别标记与先前存储的标记进行比较。 当第一检测信号被断言并且同时检测到第二信号模式比较和交易识别标记比较两者的匹配时，匹配信号被断言。 实现该方法的电路：当在总线上检测到第一信号模式时，第一比较电路确定第一检测信号。 第一存储电路存储已经被确认的第一检测信号的记录。 当检测到第一信号模式时，第二存储电路存储总线上存在的事务识别标记。 第二比较电路将总线上的信号模式与存储的信号模式进行比较，并且第三比较电路将存在于总线上的事务识别标记与存储在第二存储电路中的标记进行比较。 当第二和第三比较电路同时指示匹配并且第一存储电路指示先前检测到第一信号模式时，输出产生电路断言匹配信号。
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公开(公告)号：US5881217A
公开(公告)日：1999-03-09
申请号：US758606
申请日：1996-11-27
CPC分类号： G06F7/764 , G06F7/02 , G06F9/30043 , G06F9/30098 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Method for decoding inputs in a programmable state machine, including the following steps: bit-wise comparing state machine inputs with select information to produce bit-wise comparison results; determining the logical AND of the bit-wise comparison results; and determining the logical EXCLUSIVE OR of a negate indicator and the logical AND. In a further embodiment, a step of bit-wise ORing the comparison results with mask information is performed before the logical AND step. Circuitry for implementing the method: A bit-wise comparator has two sets of inputs. Its first set of inputs is coupled to state machine input signals. Its second set of inputs is coupled to select information. It is operable to produce bit-wise comparator outputs that indicate the results of bit-wise comparing the state machine input signals with the select information. AND circuitry has an AND circuitry output to indicate the logical AND of the comparator outputs. An EXCLUSIVE OR gate has its first input coupled to the AND circuitry output and has its second input coupled to a negate indicator. The output of the EXCLUSIVE OR gate constitutes the output of the inventive input comparison circuitry. In further embodiments, bit-wise OR circuitry may be interposed between the comparator and the AND circuitry. Such bit-wise OR circuitry may be used for masking by coupling its first set of inputs to the comparator outputs and coupling its second set of inputs to mask information. In the latter embodiment, the bit-wise results of the OR circuitry are ANDed by the AND circuitry.
摘要翻译： 用于对可编程状态机中的输入进行解码的方法，包括以下步骤：将状态机输入与选择信息进行比特比较，以产生逐位比较结果; 确定比特比较结果的逻辑AND; 并且确定否定指示符和逻辑AND的逻辑异或。 在另一实施例中，在逻辑与步骤之前执行将比较结果与掩码信息进行逐位OR比较的步骤。 实现该方法的电路：比特比较器具有两组输入。 其第一组输入端连接到状态机输入信号。 其第二组输入耦合到选择信息。 它可操作地产生逐位比较器输出，其指示将状态机输入信号与选择信息进行逐位比较的结果。 AND电路具有AND电路输出，用于指示比较器输出的逻辑AND。 独占或门的第一个输入端连接到AND电路输出，并将其第二个输入端耦合到一个否定指示器。 EXCLUSIVE OR门的输出构成本发明的输入比较电路的输出。 在另外的实施例中，可以在比较器和AND电路之间插入逐位OR电路。 这种逐位OR电路可以用于通过将其第一组输入耦合到比较器输出并将其第二组输入耦合到掩模信息来进行掩蔽。 在后一实施例中，OR电路的逐位结果由AND电路进行“与”运算。
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公开(公告)号：US07135892B2
公开(公告)日：2006-11-14
申请号：US11089577
申请日：2004-06-29
申请人： Bruce Doyle , Gregory L. Ranson
发明人： Bruce Doyle , Gregory L. Ranson
IPC分类号： G01R19/00
CPC分类号： G01R19/04
摘要： Systems, methodologies, media and other embodiments associated with peak detectors are described. One exemplary system embodiment includes a voltage peak detector comprising a first detector logic configured to detect a peak voltage of an input signal. The first detector logic has a circuit behavior that produces a leakage current that may alter the peak voltage. The system can also include a second detector logic configured to replicate the circuit behavior of the first detector logic including being configured to produce a replica leakage current that is equivalent to the leakage current. The second detector logic can be operably connected to the first detector logic to cause the replica leakage current to negate the leakage current.
摘要翻译： 描述了与峰值检测器相关联的系统，方法，介质和其它实施例。 一个示例性系统实施例包括电压峰值检测器，其包括被配置为检测输入信号的峰值电压的第一检测器逻辑。 第一检测器逻辑具有产生可能改变峰值电压的漏电流的电路特性。 该系统还可以包括被配置为复制第一检测器逻辑的电路特性的第二检测器逻辑，包括被配置为产生等效于泄漏电流的复制泄漏电流。 第二检测器逻辑可以可操作地连接到第一检测器逻辑，以使复制漏电流消除泄漏电流。
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9.发明授权Apparatus and method for comparing a group of binary fields with an expected pattern to generate match results 失效用于将一组二进制字段与预期模式进行比较以产生匹配结果的装置和方法
公开(公告)号：US5887003A
公开(公告)日：1999-03-23
申请号：US709798
申请日：1996-09-10
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318566
摘要： Method for efficiently and flexibly comparing a group of multi-bit binary fields with a multi-bit expected pattern to generate a set of final match results, one final match result for each binary field in the group. Sets of of bit-wise comparator results are generated, one set for each binary field, by comparing each binary field with the expected pattern. Then, sets of bit-wise mask results are generated for each binary field by bit-wise masking each set of bit-wise comparator results with a mask pattern. Then, a set of preliminary match results is generated. Each preliminary match result is equal to the logical AND of all bits making up the bit-wise mask result set for the corresponding binary field. Then, a set of secondary match results is generated by negating all of the preliminary match results if a negate indicator is asserted. Finally, a set of final match results is generated, one final match result for each binary field, by individually gating all of the secondary match results with a separate enable indicator for each binary field. The invention includes an M.times.N comparator matrix for accomplishing the just-described method. The invention also includes circuitry for comparing N binary fields with an expected pattern to generate N comparison results.
摘要翻译： 用于将一组多位二进制字段与多位预期模式进行有效和灵活比较以产生一组最终匹配结果的方法，该组中的每个二进制字段的一个最终匹配结果。 通过将每个二进制字段与预期模式进行比较，生成一组逐位比较器结果，一组用于每个二进制字段。 然后，通过用掩模图案逐位屏蔽每组逐位比较器结果，为每个二进制字段生成逐位掩码结果集。 然后，产生一组初步匹配结果。 每个初步匹配结果等于构成相应二进制字段的逐位掩码结果集的所有位的逻辑“与”。 然后，如果确定了否定指示符，则通过否定所有初步匹配结果来生成一组二次匹配结果。 最后，通过使用每个二进制字段的单独的使能指示器单独选通所有辅助匹配结果，生成一组最终匹配结果，每个二进制字段的最终匹配结果。 本发明包括用于实现刚才描述的方法的MxN比较器矩阵。 本发明还包括用于将N个二进制域与预期模式进行比较以产生N个比较结果的电路。
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