公开(公告)号：US5867644A

公开(公告)日：1999-02-02

申请号：US711491

申请日：1996-09-10

申请人： Gregory L. Ranson ,  John W. Bockhaus ,  Gregg B. Lesartre ,  Russell C. Brockmann ,  Robert E. Naas ,  Jonathan P. Lotz ,  Douglas B. Hunt ,  Patrick Knebel ,  Paul L. Perez ,  Steven T. Mangelsdorf

发明人： Gregory L. Ranson ,  John W. Bockhaus ,  Gregg B. Lesartre ,  Russell C. Brockmann ,  Robert E. Naas ,  Jonathan P. Lotz ,  Douglas B. Hunt ,  Patrick Knebel ,  Paul L. Perez ,  Steven T. Mangelsdorf

IPC分类号： G06F11/36 ,  G06F11/00

CPC分类号： G06F11/3648 ,  G06F11/364

摘要： User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.

摘要翻译： 用户可配置的诊断硬件包含微处理器，用于调试和监视微处理器的性能。 使用方法 可编程状态机耦合到片上和片外输入源。 状态机可以被编程为寻找由输入源呈现的信号模式，并且通过将某些控制信息驱动到状态机输出总线上来响应定义的模式（或定义的模式的序列）的出现。 耦合到输出总线的片上设备采用由总线指示的用户可定义的动作。 输入源包括位于微处理器的功能块内的用户可配置比较器。 比较器耦合到微处理器内的存储元件，并且被配置为监视节点以确定节点的状态是否与包含在存储元件中的数据匹配。 通过改变存储元件中的数据，程序员可以改变比较节点状态的信息，以及进行比较的方法。 输出设备包括计数器。 计数器输出可以用作状态机输入，因此可以将一个事件定义为发生一定次数的不同事件的功能。 输出设备还包括用于产生内部和外部触发的电路。 用户可配置的多路复用器电路可以用于将用户可选择的信号从微处理器传送到芯片的输出焊盘，并且选择要用作状态机输入的各种内部信号。

公开(公告)号：US5956476A

公开(公告)日：1999-09-21

申请号：US741563

申请日：1996-10-31

申请人： Gregory L. Ranson ,  Russell C. Brockmann ,  Robert E. Naas

发明人： Gregory L. Ranson ,  Russell C. Brockmann ,  Robert E. Naas

IPC分类号： G06F11/14 ,  G06F13/16 ,  G06F13/20

CPC分类号： G06F11/1443

摘要： Method for detecting when first and second signal patterns have occurred on a split-transaction bus having transaction identifying indicia: Signal patterns occurring on the bus are compared with a first stored signal pattern. If a match is detected, the transaction identifying indicia that were associated on the bus with the first signal pattern are stored, and a first detection signal is asserted and held asserted. Signal patterns on the bus are then compared with a second stored signal pattern, and transaction identifying indicia occurring on the bus are compared with the indicia previously stored. A match signal is asserted when the first detection signal is asserted and, simultaneously, matches are detected for both of the second signal pattern comparison and the transaction identifying indicia comparison. Circuitry for implementing the method: First comparison circuitry asserts a first detection signal when a first signal pattern is detected on the bus. First storage circuitry stores a record of the first detection signal having been asserted. Second storage circuitry stores the transaction identifying indicia present on the bus when the first signal pattern is detected. Second comparison circuitry compares the signal patterns on the bus with a stored signal pattern, and third comparison circuitry compares the transaction identifying indicia present on the bus with the indicia stored in the second storage circuitry. When the second and third comparison circuitries simultaneously indicate matches and the first storage circuitry indicates that the first signal pattern was previously detected, output generation circuitry asserts a match signal.

摘要翻译： 用于检测在具有事务识别标记的分割事务总线上何时发生第一和第二信号模式的方法：将总线上发生的信号模式与第一存储的信号模式进行比较。 如果检测到匹配，则存储与总线上与第一信号模式相关联的交易识别标记，并且第一检测信号被断言并保持断言。 然后将总线上的信号模式与第二存储的信号模式进行比较，并将总线上发生的事务识别标记与先前存储的标记进行比较。 当第一检测信号被断言并且同时检测到第二信号模式比较和交易识别标记比较两者的匹配时，匹配信号被断言。 实现该方法的电路：当在总线上检测到第一信号模式时，第一比较电路确定第一检测信号。 第一存储电路存储已经被确认的第一检测信号的记录。 当检测到第一信号模式时，第二存储电路存储总线上存在的事务识别标记。 第二比较电路将总线上的信号模式与存储的信号模式进行比较，并且第三比较电路将存在于总线上的事务识别标记与存储在第二存储电路中的标记进行比较。 当第二和第三比较电路同时指示匹配并且第一存储电路指示先前检测到第一信号模式时，输出产生电路断言匹配信号。

公开(公告)号：US5881217A

公开(公告)日：1999-03-09

申请号：US758606

申请日：1996-11-27

申请人： Gregory L. Ranson ,  Russell C. Brockmann

发明人： Gregory L. Ranson ,  Russell C. Brockmann

IPC分类号： G06F7/02 ,  G06F7/76 ,  G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F11/27

CPC分类号： G06F7/764 ,  G06F7/02 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Method for decoding inputs in a programmable state machine, including the following steps: bit-wise comparing state machine inputs with select information to produce bit-wise comparison results; determining the logical AND of the bit-wise comparison results; and determining the logical EXCLUSIVE OR of a negate indicator and the logical AND. In a further embodiment, a step of bit-wise ORing the comparison results with mask information is performed before the logical AND step. Circuitry for implementing the method: A bit-wise comparator has two sets of inputs. Its first set of inputs is coupled to state machine input signals. Its second set of inputs is coupled to select information. It is operable to produce bit-wise comparator outputs that indicate the results of bit-wise comparing the state machine input signals with the select information. AND circuitry has an AND circuitry output to indicate the logical AND of the comparator outputs. An EXCLUSIVE OR gate has its first input coupled to the AND circuitry output and has its second input coupled to a negate indicator. The output of the EXCLUSIVE OR gate constitutes the output of the inventive input comparison circuitry. In further embodiments, bit-wise OR circuitry may be interposed between the comparator and the AND circuitry. Such bit-wise OR circuitry may be used for masking by coupling its first set of inputs to the comparator outputs and coupling its second set of inputs to mask information. In the latter embodiment, the bit-wise results of the OR circuitry are ANDed by the AND circuitry.

摘要翻译： 用于对可编程状态机中的输入进行解码的方法，包括以下步骤：将状态机输入与选择信息进行比特比较，以产生逐位比较结果; 确定比特比较结果的逻辑AND; 并且确定否定指示符和逻辑AND的逻辑异或。 在另一实施例中，在逻辑与步骤之前执行将比较结果与掩码信息进行逐位OR比较的步骤。 实现该方法的电路：比特比较器具有两组输入。 其第一组输入端连接到状态机输入信号。 其第二组输入耦合到选择信息。 它可操作地产生逐位比较器输出，其指示将状态机输入信号与选择信息进行逐位比较的结果。 AND电路具有AND电路输出，用于指示比较器输出的逻辑AND。 独占或门的第一个输入端连接到AND电路输出，并将其第二个输入端耦合到一个否定指示器。 EXCLUSIVE OR门的输出构成本发明的输入比较电路的输出。 在另外的实施例中，可以在比较器和AND电路之间插入逐位OR电路。 这种逐位OR电路可以用于通过将其第一组输入耦合到比较器输出并将其第二组输入耦合到掩模信息来进行掩蔽。 在后一实施例中，OR电路的逐位结果由AND电路进行“与”运算。

公开(公告)号：US5881224A

公开(公告)日：1999-03-09

申请号：US711574

申请日：1996-09-10

申请人： Gregory L. Ranson ,  Gregg B. Lesartre ,  Russell C. Brockmann

发明人： Gregory L. Ranson ,  Gregg B. Lesartre ,  Russell C. Brockmann

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/38 ,  G06F11/00 ,  G06F11/267 ,  G06F11/34

CPC分类号： G06F9/3865 ,  G06F11/076 ,  G06F11/2236 ,  G06F11/348 ,  G06F9/30032 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F11/3409 ,  G06F2201/88

摘要： In one embodiment, the invention includes a method of tracking events in a microprocessor that can retire more than one instruction during a clock cycle. A set of match results is generated during each clock cycle, one match result for each retiring instruction. Each of the match results indicates whether the corresponding retiring instruction matched a criterion. Then, the total number of retiring instruction that matched the criterion is determined by adding the asserted match results to generate a sum. A counter is incremented by the sum. In another embodiment, the invention includes circuitry for implementing the just-described method. Match generator circuitry is provided for generating a set of match results during each clock cycle, one match result for each retiring instruction. The outputs of the match generator circuitry are supplied to adder circuitry. The adder circuitry is operable to determine the number of said match results that are asserted and to represent the number as a sum via a set of adder circuitry outputs. A counter having a set of adder circuitry inputs is coupled to adder circuitry outputs. The counter is operable to increment its count by the sum represented by the adder circuitry outputs. In further embodiments, a multiplexer is interposed between the adder circuitry and the counter. The multiplexer has a first set of inputs coupled to the adder circuitry outputs, and a second set of inputs coupled to a source of the value "1." The multiplexer is operable to present either the first or second inputs on its outputs responsive to a select signal. The multiplexer has its outputs coupled to the increment inputs of the counter.

摘要翻译： 在一个实施例中，本发明包括跟踪微处理器中的事件的方法，其可以在时钟周期期间退出多于一个指令。 在每个时钟周期内产生一组匹配结果，每个退出指令一个匹配结果。 每个匹配结果指示相应的退出指令是否匹配标准。 然后，通过添加所断言的匹配结果以产生和来确定与标准匹配的退休指令的总数。 一个计数器增加一个和。 在另一个实施例中，本发明包括用于实现刚刚描述的方法的电路。 匹配发生器电路被提供用于在每个时钟周期期间产生一组匹配结果，每个退出指令的一个匹配结果。 匹配发生器电路的输出被提供给加法器电路。 加法器电路可操作以确定所确定的所述匹配结果的数量，并且经由一组加法器电路输出将数字表示为和。 具有一组加法器电路输入的计数器耦合到加法器电路输出。 计数器可操作地将其计数增加由加法器电路输出表示的和。 在另外的实施例中，多路复用器插在加法器电路和计数器之间。 多路复用器具有耦合到加法器电路输出的第一组输入和耦合到值“1”的源的第二组输入。 多路复用器可操作以响应于选择信号在其输出上呈现第一或第二输入。 多路复用器的输出端与计数器的增量输入相连。

公开(公告)号：US5887003A

公开(公告)日：1999-03-23

申请号：US709798

申请日：1996-09-10

申请人： Gregory L. Ranson ,  Russell C. Brockmann ,  Douglas B. Hunt

发明人： Gregory L. Ranson ,  Russell C. Brockmann ,  Douglas B. Hunt

IPC分类号： G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318566

摘要： Method for efficiently and flexibly comparing a group of multi-bit binary fields with a multi-bit expected pattern to generate a set of final match results, one final match result for each binary field in the group. Sets of of bit-wise comparator results are generated, one set for each binary field, by comparing each binary field with the expected pattern. Then, sets of bit-wise mask results are generated for each binary field by bit-wise masking each set of bit-wise comparator results with a mask pattern. Then, a set of preliminary match results is generated. Each preliminary match result is equal to the logical AND of all bits making up the bit-wise mask result set for the corresponding binary field. Then, a set of secondary match results is generated by negating all of the preliminary match results if a negate indicator is asserted. Finally, a set of final match results is generated, one final match result for each binary field, by individually gating all of the secondary match results with a separate enable indicator for each binary field. The invention includes an M.times.N comparator matrix for accomplishing the just-described method. The invention also includes circuitry for comparing N binary fields with an expected pattern to generate N comparison results.

摘要翻译： 用于将一组多位二进制字段与多位预期模式进行有效和灵活比较以产生一组最终匹配结果的方法，该组中的每个二进制字段的一个最终匹配结果。 通过将每个二进制字段与预期模式进行比较，生成一组逐位比较器结果，一组用于每个二进制字段。 然后，通过用掩模图案逐位屏蔽每组逐位比较器结果，为每个二进制字段生成逐位掩码结果集。 然后，产生一组初步匹配结果。 每个初步匹配结果等于构成相应二进制字段的逐位掩码结果集的所有位的逻辑“与”。 然后，如果确定了否定指示符，则通过否定所有初步匹配结果来生成一组二次匹配结果。 最后，通过使用每个二进制字段的单独的使能指示器单独选通所有辅助匹配结果，生成一组最终匹配结果，每个二进制字段的最终匹配结果。 本发明包括用于实现刚才描述的方法的MxN比较器矩阵。 本发明还包括用于将N个二进制域与预期模式进行比较以产生N个比较结果的电路。

公开(公告)号：US06789186B1

公开(公告)日：2004-09-07

申请号：US09507038

申请日：2000-02-18

申请人： Russell C. Brockmann ,  Kevin David Safford ,  Jane Wang ,  Chris Poirier

发明人： Russell C. Brockmann ,  Kevin David Safford ,  Jane Wang ,  Chris Poirier

IPC分类号： G06G900

CPC分类号： G06F9/3804 ,  G06F9/30174

摘要： A method and apparatus are provided for improving the rate at which macroinstructions are transformed into corresponding microinstructions. Encoding is added to a microcode storage device. The encoding indicates that a microinstruction flow will end in a determined number of cycles. The number of cycles is determined by the number of canceled instructions in a processing pipeline that would be introduced if no flow length prediction was used. For flow lengths less than a determined number of cycles, a hint bit is used in an entry point structure. For flow lengths greater than a determined length, a hint bit is encoded at a third line from an end of the microinstruction flow. Using this method, flows of any length can be hinted. Furthermore, flows that do not originate from the entry point structure can also be hinted. The method reduces the number of hint bits that are needed in the entry point structure and provides for better prediction.

摘要翻译： 提供了一种方法和装置，用于提高宏指令转换成相应微指令的速率。 编码被添加到微代码存储设备中。 编码指示微指令流将以确定的周期数结束。 循环数由在不使用流量长度预测的情况下将被引入的处理流水线中的取消指令的数量来确定。 对于小于一定数量的循环的流量长度，在入口点结构中使用提示位。 对于大于确定长度的流量长度，提示位在微指令流的末尾的第三行编码。 使用这种方法，可以暗示任何长度的流。 此外，也可以暗示不源于入口点结构的流。 该方法减少了入口点结构中所需的提示位的数量，并提供了更好的预测。

公开(公告)号：US06625759B1

公开(公告)日：2003-09-23

申请号：US09502366

申请日：2000-02-18

申请人： Jeremy Petsinger ,  Kevin David Safford ,  Karl P. Brummel ,  Russell C. Brockmann ,  Bruce A. Long ,  Patrick Knebel

发明人： Jeremy Petsinger ,  Kevin David Safford ,  Karl P. Brummel ,  Russell C. Brockmann ,  Bruce A. Long ,  Patrick Knebel

IPC分类号： H02H305

CPC分类号： G06F11/261

摘要： A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.

摘要翻译： 一种方法和装置检查微码机中央处理器单元（CPU）行为模型的细粒度正确性。 宏指令被分解为微指令，并且每个微指令都被顺序执行。 微指令序列由模拟的微指令测序仪确定，使用动态执行信息，包括在微指令序列中执行先前微指令的信息。 在每个微指令的执行结束时，将参考状态与行为模型的相应状态进行比较，并且注意到任何差异。 在微指令序列中执行所有微指令之后，将参考状态与行为模型的相应状态进行比较，并记录任何差异。

公开(公告)号：US5437019A

公开(公告)日：1995-07-25

申请号：US217001

申请日：1994-03-23

申请人： Russell C. Brockmann

发明人： Russell C. Brockmann

IPC分类号： G06F13/14 ,  G06F12/06 ,  G06F12/00 ,  G06F1/00

CPC分类号： G06F12/0676

摘要： Each card slot in a computer system receives a different ordering of address lines than each of the other card slots so that the ordering of the address lines at each card slot is indicative of its physical address relative to the other card slots. Means responsive to codes provided on at least selected ones of the address lines for establishing the hard and soft physical addresses of cards to be inserted into the slots may be provided.

摘要翻译： 计算机系统中的每个卡插槽接收与每个其他卡插槽不同的地址线顺序，使得每个卡槽处的地址线的排序指示其相对于其它卡槽的物理地址。 可以提供响应于至少选择的地址线中提供的代码来建立要插入到插槽中的卡的硬和软物理地址的装置。

公开(公告)号：US5287477A

公开(公告)日：1994-02-15

申请号：US741703

申请日：1991-08-07

申请人： Leith L. Johnson ,  Russell C. Brockmann ,  William S. Jaffe

发明人： Leith L. Johnson ,  Russell C. Brockmann ,  William S. Jaffe

IPC分类号： G06F12/06 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/161 ,  G06F12/0607

摘要： A method and apparatus to improve memory performance in a computer bus system. Memory is divided into interleaved blocks and memory addresses are mapped into block identification numbers. Master devices keep track of which parts of memory are busy by storing memory block identification numbers in local queues whenever memory is accessed. Block identification numbers are removed from local queues when the memory transaction is complete. Master devices arbitrate for access to the bus for memory transactions only if the target memory block identification number is not in the local queue.

摘要翻译： 一种用于改善计算机总线系统中的存储器性能的方法和装置。 存储器被划分为交错块，存储器地址被映射到块标识号。 当存储器被访问时，主设备通过将存储器块识别号码存储在本地队列中来跟踪存储器的哪个部分正在占用。 当内存事务完成时，块标识号从本地队列中删除。 只有当目标存储器块标识号不在本地队列中时，主设备仲裁才能访问总线用于存储器事务。

公开(公告)号：US5265223A

公开(公告)日：1993-11-23

申请号：US924423

申请日：1992-07-31

申请人： Russell C. Brockmann ,  William S. Jaffe

发明人： Russell C. Brockmann ,  William S. Jaffe

IPC分类号： G06F13/368 ,  G06F13/00 ,  G06F13/36

CPC分类号： G06F13/368

摘要： A method and circuitry for controlling priority of devices contending for access to a data communications link. Each device capable of contending for access contains a priority register which indicates the relative priority of every device capable of contending for access. After gaining access to the link, a device may optionally signal to all devices to update priority. When priority is updated, the device signaling priority update is moved to lowest priority. Inhibiting the signal to update priority permits a device to maintain priority. Systems using the method may be configured with a fair arbitration protocol (least recently accessed has highest priority), with fixed priority protocol, or with priority protocols that can be modified in real time.

摘要翻译： 一种用于控制竞争访问数据通信链路的设备的优先级的方法和电路。 能够争取访问的每个设备都包含优先级寄存器，该优先级寄存器指示每个能够竞争访问的设备的相对优先级。 在访问链接之后，设备可以可选地向所有设备发信号以更新优先级。 当优先级更新时，设备信令优先级更新被移动到最低优先级。 抑制信号更新优先级允许设备保持优先级。 使用该方法的系统可以配置有公平的仲裁协议（最近访问的具有最高优先级），具有固定优先级协议，或者可以实时修改的优先级协议。