Testing and error recovery across multiple switching fabrics
    1.
    发明授权
    Testing and error recovery across multiple switching fabrics 有权
    跨多个交换结构的测试和错误恢复

    公开(公告)号:US07876693B2

    公开(公告)日:2011-01-25

    申请号:US10453976

    申请日:2003-06-04

    IPC分类号: H04J3/14

    摘要: A packet-based traffic switching system with error detection and correction without taking the system offline. The system tests offline paths without interfering with other online paths. Also, the system tests online paths even while no data cell traffic is sent over the paths. The system responds to the addition or removal of paths or path components without interrupting cell traffic. The system detects and selectively flushes defective paths without impacting paths that are working properly. The system initializes new switching fabrics automatically without using software to set values. Thus, the system tests online paths and corrects errors without going offline.

    摘要翻译: 一种基于分组的业务交换系统,具有错误检测和校正功能,无需系统脱机。 系统测试离线路径,而不会干扰其他在线路径。 此外,即使在路径上没有发送数据信元流量的情况下,系统也会测试在线路径。 系统响应添加或删除路径或路径组件,而不会中断单元流量。 系统检测并有选择地刷新故障路径,而不影响正常工作的路径。 系统自动初始化新的交换结构,而不用软件设置值。 因此,系统会测试在线路径并纠正错误,而无需离线。

    Using reassembly queue sets for packet reassembly
    2.
    发明授权
    Using reassembly queue sets for packet reassembly 有权
    使用重组队列来进行分组重组

    公开(公告)号:US07394822B2

    公开(公告)日:2008-07-01

    申请号:US10454298

    申请日:2003-06-04

    IPC分类号: H04L12/28 H04L12/56 H04J3/24

    摘要: A system for efficiently reassembling packets from cells received on independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by skipping the fabrics in striping and reassembly sequences. When fabrics are added, the fabrics are included in the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

    摘要翻译: 一种用于根据串行高速接口(HSI)协议在独立交换结构上接收的小区有效地重组分组的系统。 该系统包括冗余,其中可以通过以条带化和重新组装顺序跳过织物来去除织物。 当织物加入时,织物被包括在条纹和重新组装序列中。 该系统有效地部分地是由单元顺序传输跨多个结构的单元。 从而利用了全面的带宽,而无需重新排序开销。 由于数据包是跨所有可用的织物分条,因此整个结构之间的负载是平衡的。

    Optimal load balancing across multiple switching fabrics
    3.
    发明授权
    Optimal load balancing across multiple switching fabrics 有权
    跨多个交换结构的最佳负载平衡

    公开(公告)号:US07242691B2

    公开(公告)日:2007-07-10

    申请号:US10454167

    申请日:2003-06-04

    IPC分类号: H01L12/56 H01L12/28

    摘要: A system for efficiently sending cells in-order to independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by deleting the fabrics from striping and reassembly sequences. When fabrics are added, the fabrics are added to the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

    摘要翻译: 根据串行高速接口(HSI)协议,有效地将单元按顺序发送到独立的交换结构的系统。 该系统包括冗余,其中可以通过从条带化和重新组装序列中删除织物来去除织物。 当加入织物时,将织物加入到条纹和重新组装序列中。 该系统有效地部分地是由单元顺序传输跨多个结构的单元。 从而利用了全面的带宽,而无需重新排序开销。 由于数据包是跨所有可用的织物分条,因此整个结构之间的负载是平衡的。

    Flow control in a distributed scalable, shared memory switching fabric system
    4.
    发明授权
    Flow control in a distributed scalable, shared memory switching fabric system 有权
    分布式可扩展共享内存交换结构体系中的流控制

    公开(公告)号:US07525917B2

    公开(公告)日:2009-04-28

    申请号:US10453975

    申请日:2003-06-04

    IPC分类号: G01R31/08 H04L12/28

    摘要: A traffic control system and method with flow control aggregation. The system includes a switching fabric and an ingress module. The switching fabric includes read counters that are associated with a plurality of queues. The read counters represent an aggregated number of cells dequeued from respective queues since a previous flow control message (FCM) was sent to the ingress module. The read counters are reset when a FCM is created. The ingress module includes write counters that are associated with the queues. The write counters are incremented each time a cell is sent to the respective queues. The write counters are decremented in accordance with the FCM when the FCM is received. Also, read counters for one or more queues are aggregated into a single FCM.

    摘要翻译: 一种具有流量控制聚合的交通控制系统和方法。 该系统包括交换结构和入口模块。 交换结构包括与多个队列相关联的读取计数器。 读取计数器表示从先前流控制消息(FCM)发送到入口模块的从相应队列出队的单元的聚合数。 读取计数器在创建FCM时被重置。 入口模块包括与队列相关联的写入计数器。 每当将单元发送到相应的队列时,写计数器递增。 当接收到FCM时,写计数器根据FCM递减。 此外,一个或多个队列的读取计数器会聚合到一个FCM中。

    Multicast packet queuing
    5.
    发明授权
    Multicast packet queuing 有权
    组播数据包排队

    公开(公告)号:US07609693B2

    公开(公告)日:2009-10-27

    申请号:US10443505

    申请日:2003-05-22

    IPC分类号: H04L12/28

    摘要: A traffic forwarding system that uses a multicast start-of-packet (SOP) pointer to enqueue a multicast packet in packet queues. The system receives cells, assigns pointers to the cells, and stores the received cells in memory. The system assigns multicast SOP pointers to multicast SOP cells. The system reassembles cells into packets and enqueues the packets in packet queues for forwarding. A multicast packet is enqueued in a plurality of packet queues. The memory in which the multicast packet is stored is released after the multicast packet is dequeued from each of the plurality of packet queues.

    摘要翻译: 一种使用组播开始分组(SOP)指针将数据包队列中的组播数据包排入队列的流量转发系统。 系统接收单元,指定单元格的指针,并将接收到的单元格存储在存储器中。 系统将组播SOP指针分配给组播SOP单元。 系统将单元重新组合成数据包,并将数据包队列中的数据包排入队列中进行转发。 多播分组排队在多个分组队列中。 在组播分组从多个分组队列中的每一个出队后,释放其中存储多播分组的存储器。

    High-speed chip-to-chip communication interface
    6.
    发明授权
    High-speed chip-to-chip communication interface 有权
    高速芯片到芯片通信接口

    公开(公告)号:US07180949B2

    公开(公告)日:2007-02-20

    申请号:US10439571

    申请日:2003-05-16

    IPC分类号: H04L27/00 H04L25/00 H04L25/06

    摘要: A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.

    摘要翻译: 公开了一种用于在集成电路之间传送数据的高速并行接口。 该接口由发射机和接收机对以及耦合到发射机和接收机对的单端并行互连总线来实现。 与通过差分信号线发送小的摆动信号相反,发射器在单端并行互连总线上全速摆放数据到接收机。 本发明可以用不消耗大的管芯面积的简单的CMOS电路来实现。 因此,可以在单个芯片上实现许多链路接口以提供大的数据带宽。

    High-speed chip-to-chip communication interface with signal trace routing and phase offset detection
    7.
    发明授权
    High-speed chip-to-chip communication interface with signal trace routing and phase offset detection 有权
    具有信号跟踪路由和相位偏移检测的高速芯片到芯片通信接口

    公开(公告)号:US07134056B2

    公开(公告)日:2006-11-07

    申请号:US10439566

    申请日:2003-05-16

    IPC分类号: G06F11/00 G06F13/14

    摘要: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

    摘要翻译: 公开了一种用于在集成电路之间传送数据的高速并行接口。 在一个实施例中,发射机控制器每167Mhz时钟周期接收40位宽的数据,接收器控制器每167 Mhz时钟周期传送40位宽的数据,互连总线在333的每个转换时传输10位宽的数据 Mhz时钟周期。 在另一个实施例中,发射机控制器每167 Mhz时钟周期接受32位宽数据,接收机控制器每167 Mhz时钟周期传输32位宽数据,本实施例的互连总线在每次转换时都会传输8位宽数据 一个333 Mhz的时钟周期。 发射器接口的输出引脚可以连接到接收器接口的任何输入引脚。 此外,高速并行接口不需要接收机的内部时钟和总线时钟信号之间的固定的相位关系。

    Flexible multilevel output traffic control
    8.
    发明授权
    Flexible multilevel output traffic control 有权
    灵活的多级输出流量控制

    公开(公告)号:US07474668B2

    公开(公告)日:2009-01-06

    申请号:US10439681

    申请日:2003-05-16

    IPC分类号: H04L12/28 H04L12/56

    摘要: A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

    摘要翻译: 实施两级速率整形和调度系统和方法来控制至少一个输出接口的流量流。 该系统和方法包括最初将进入的分组排队到类型特定的队列中,并将各个速率整形规则应用于每个队列。 执行第一阶段仲裁以确定流量如何从类型特定队列排队到特定于接口的队列。 获胜仲裁和传递应用速率整形规则的数据包在接口特定的队列中排队。 速率整形规则应用于特定于接口的队列。 特定于接口的队列通过优先级和优先级特定进一步区分,并且将接口特定的速率整形规则应用于每个队列。 执行第二阶段仲裁以确定针对相同输出接口的不同优先级流量如何响应于特定于接口的请求而出列。

    Active flow facial cleanser
    9.
    发明授权

    公开(公告)号:US11382466B1

    公开(公告)日:2022-07-12

    申请号:US17387649

    申请日:2021-07-28

    摘要: A method for cleansing a desired skin surface, and a device therefor, can include a base to house a jar for the cleansing liquid, a jar for the removed liquid and debris, a pump to deliver the cleansing liquid to a wand applicator, and a pump to suction the cleansing liquid and debris removed from the desired skin surface. The two pumps can be driven by separate motors to allow a user to separately control the amount of liquid dispensed and the magnitude of the suction force applied. The device can also include an infusion enhancer that assists in the opening of the pores of the desired skin surface or by tightening the desired skin surface. The device can further include a self-cleaning tip that allows a cleaning solution to be immediately recycled through the system into the jar for the removed liquid and debris.

    LADDER FLAG STORAGE DEVICE
    10.
    发明申请
    LADDER FLAG STORAGE DEVICE 审中-公开
    梯子标志存储设备

    公开(公告)号:US20160168909A1

    公开(公告)日:2016-06-16

    申请号:US14692694

    申请日:2015-04-21

    申请人: Eric Anderson

    发明人: Eric Anderson

    IPC分类号: E06C7/00 G09F17/00 F16M13/02

    摘要: The present disclosure relates to a ladder-mountable storage device for storing and retractably deploying a flag. The flag can be displayed on the end of a ladder to warn onlookers. If used on the end of a ladder extending from a vehicle, the flag warns drivers to keep a safe distance, for example. The ladder-mountable storage device can also be attached to the top of ladders placed alongside buildings and other structures.

    摘要翻译: 本公开涉及一种用于存储和可缩回地展开标志的梯形安装式存储装置。 标志可以显示在梯子的末端,以警告旁观者。 如果在从车辆延伸的梯子的末端使用,则标志警告司机保持安全距离。 梯形安装式存储装置也可以连接到沿着建筑物和其他结构放置的梯子的顶部。