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公开(公告)号：US08453124B2
公开(公告)日：2013-05-28
申请号：US12645687
申请日：2009-12-23
申请人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
发明人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3409
摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.
摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。
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公开(公告)号：US20110154298A1
公开(公告)日：2011-06-23
申请号：US12645687
申请日：2009-12-23
申请人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
发明人： Gregory W. Alexander , Jane Bartik , Michael Billeci , David Hutton , Christian Jacobi , Jang-Soo Lee , Eric Schwarz , Chung-Lung Shum , Phil C. Yeh
IPC分类号： G06F9/44
CPC分类号： G06F11/348 , G06F11/3409
摘要： A system and method for collecting instrumentation data in a processor with a pipelined instruction execution stages arranged in an out-of-order execution architecture. One instruction group in a Global Completion Table is marked as a tagged group. Instrumentation data is stored for processing stages processing instructions associated with the tagged group. Sample signal pulses trigger a determination of whether the tagged group is the next-to-complete instruction group. When the sample pulse occurs at a time when the tagged group is the next-to-complete group, the instrumentation data is written as an output. Instrumentation data present during sample pulses that occur when the tagged group is not the next-to-complete group is optionally discarded. Sample pulses are generated at a rate equal to the desired sample rate times the number of groups in the global completion table to better ensure occurrence of a next-to-complete tagged group.
摘要翻译： 一种用处理器收集仪器数据的系统和方法，其中流水线指令执行阶段以无序执行体系结构排列。 全局完成表中的一个指令组被标记为标记组。 存储用于与标记组相关联的处理阶段处理指令的仪表数据。 采样信号脉冲触发确定标记的组是否是下一个完成指令组。 当标记的组是下一个完成组时，当采样脉冲发生时，仪表数据被写为输出。 当标记的组不是下一个到完整的组时发生的采样脉冲期间存在的仪器数据被任选地丢弃。 以等于所需采样率的速率乘以采样脉冲乘以全局完成表中的组数，以更好地确保下一个到完整标记组的发生。
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公开(公告)号：US20060179290A1
公开(公告)日：2006-08-10
申请号：US11055193
申请日：2005-02-10
申请人： Fadi Busaba , Michael Mack , John Rell , Eric Schwarz , Chung-Lung Shum , Timothy Slegel , Scott Swaney , Sheryll Veneracion
发明人： Fadi Busaba , Michael Mack , John Rell , Eric Schwarz , Chung-Lung Shum , Timothy Slegel , Scott Swaney , Sheryll Veneracion
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3863 , G06F2209/481
摘要： A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.
摘要翻译： 一种用于创建精确异常的方法，包括检查指向引起异常的指令。 检查点导致当前检查点状态。 当前检查点状态被锁定。 确定多个寄存器中的任一个是否需要恢复到当前检查点状态。 响应于指示一个或多个寄存器需要恢复的确定结果，一个或多个寄存器恢复到当前检查点状态。 执行单元在异常处理程序或下一个顺序指令下重新启动，取决于是否为异常启用陷阱。
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公开(公告)号：US09244654B2
公开(公告)日：2016-01-26
申请号：US13544338
申请日：2012-07-09
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点操作数，并对至少一个十进制浮点运算执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US20120278374A1
公开(公告)日：2012-11-01
申请号：US13544338
申请日：2012-07-09
IPC分类号： G06F11/00
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US08219605B2
公开(公告)日：2012-07-10
申请号：US12789765
申请日：2010-05-28
IPC分类号： G06F11/00
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US20110296229A1
公开(公告)日：2011-12-01
申请号：US12789765
申请日：2010-05-28
IPC分类号： G06F11/07
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译： 用于检测十进制浮点数据处理异常的系统和方法。 一个处理器接受至少一个十进制浮点运算符，并在至少一个十进制浮点运算符上执行十进制浮点运算，以产生一个十进制浮点运算结果。 确定十进制浮点结果是否不能保持优选的量子。 优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。 提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。 可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。
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公开(公告)号：US09104399B2
公开(公告)日：2015-08-11
申请号：US12645716
申请日：2009-12-23
申请人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： Fadi Busaba , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。
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公开(公告)号：US20110153991A1
公开(公告)日：2011-06-23
申请号：US12645716
申请日：2009-12-23
申请人： FADI BUSABA , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
发明人： FADI BUSABA , Brian Curran , Lee Eisen , Christian Jacobi , David A. Schroter , Eric Schwarz
CPC分类号： G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/3836 , G06F9/3867
摘要： A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
摘要翻译： 一种用于向处理流水线结构排列的多个处理部分发出处理器指令的系统和方法。 多个处理部分包括具有流水线长度的第一执行单元和对由第一执行单元产生的数据进行操作的第二执行单元。 指令发布单元接受对于第一执行单元和第二执行单元破解为相应微操作的复杂指令。 指令发布单元向第一执行单元发出第一微操作以产生中间数据。 然后，指令发布单元延迟与第一执行单元的处理流水线长度对应的时间段。 在延迟之后，向第二执行单元发出第二个微操作。
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10.发明申请TRIGGERING WORKAROUND CAPABILITIES BASED ON EVENTS ACTIVE IN A PROCESSOR PIPELINE 有权根据处理器管道中活动的事件触发替代能力公开(公告)号：US20110154107A1
公开(公告)日：2011-06-23
申请号：US12645771
申请日：2009-12-23
申请人： GREGORY W. ALEXANDER , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： GREGORY W. ALEXANDER , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw.
摘要翻译： 处理器中的处理缺陷的方法，信息处理系统和处理器。 从存储器位置获取至少一个指令。 至少一条指令被解码。 响应于解码，将操作码比较操作与至少一个操作码比较寄存器中的至少一个指令和一组值进行比较。 该指令用基于操作码比较操作的模式标记。 该模式表示该指令与处理缺陷相关联。
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