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1.发明授权Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions 有权分支目标预加载使用多路复用器和散列电路来减少不正确的分支预测公开(公告)号：US09519480B2
公开(公告)日：2016-12-13
申请号：US12029258
申请日：2008-02-11
申请人： Gregory W. Alexander , Anton Blanchard , Milton D. Miller, II , Todd A. Venton , Kenneth L. Wright
发明人： Gregory W. Alexander , Anton Blanchard , Milton D. Miller, II , Todd A. Venton , Kenneth L. Wright
CPC分类号： G06F9/30043 , G06F9/3005 , G06F9/3804 , G06F9/3806
摘要： A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.
摘要翻译： 系统提供复杂的分支执行硬件和基于硬件的多路复用器（MUX）来复用未来分支的提取地址和预加载的分支提取地址，以创建用于索引分支目标预测表以执行的索引散列值 处理器核心，以便通过预加载减少分支误预测。
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2.发明授权High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction 失效使用多页大小预测的高性能缓存翻译后备缓冲区（TLB）查找公开(公告)号：US08667258B2
公开(公告)日：2014-03-04
申请号：US12821723
申请日：2010-06-23
CPC分类号： G06F9/3806 , G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes.
摘要翻译： 一种具有处理器的计算机处理系统方法和装置，所述处理器采用多个用户程序之间的操作系统（O / S）多任务控制，并确保所述程序不相互干扰，所述计算处理系统具有分支多页大小 预测机构，其预测具有分支目标缓冲器（BTB）的处理流水线的指示的分支方向的分支方向和分支目标的分页目标，所述分支目标缓冲器（BTB）预测分支目标，所述分支预测机制存储最近使用的指令， 处理器，并且具有跟踪最近页面的翻译并支持多个页面大小的翻译后备缓冲器TLB机制。
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公开(公告)号：US08468325B2
公开(公告)日：2013-06-18
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.
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4.发明申请ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS 审中-公开将计数器从计数器分配到跟踪逻辑寄存器映射到基于MAPPER的指令执行的物理寄存器公开(公告)号：US20120265969A1
公开(公告)日：2012-10-18
申请号：US13450429
申请日：2012-04-18
CPC分类号： G06F9/30098 , G06F9/384
摘要： A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译： 计算机系统从当前在计数器空闲池中的多个计数器中分配特定的计数器，以计数从多个逻辑寄存器到多个物理寄存器中的特定物理寄存器的逻辑寄存器的映射的数量，响应于 通过映射器单元执行指令，将至少一个逻辑寄存器从多个逻辑寄存器映射到特定物理寄存器，其中多个计数器的数量小于多个物理寄存器的数量。 计算机系统响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。
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5.发明授权公开(公告)号：US08015362B2
公开(公告)日：2011-09-06
申请号：US12031923
申请日：2008-02-15
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F9/3812
摘要： A method for handling cache coherency includes allocating a tag when a cache line is not exclusive in a data cache for a store operation, and sending the tag and an exclusive fetch for the line to coherency logic. An invalidation request is sent within a minimum amount of time to an I-cache, preferably only if it has fetched to the line and has not been invalidated since, which request includes an address to be invalidated, the tag, and an indicator specifying the line is for a PSC operation. The method further includes comparing the request address against stored addresses of prefetched instructions, and in response to a match, sending a match indicator and the tag to an LSU, within a maximum amount of time. The match indicator is timed, relative to exclusive data return, such that the LSU can discard prefetched instructions following execution of the store operation that stores to a line subject to an exclusive data return, and for which the match is indicated.
摘要翻译： 一种用于处理高速缓存一致性的方法包括当高速缓存行在存储操作的数据高速缓存中不排斥时分配标签，以及将该标签和该行的独占提取发送到一致性逻辑。 无效请求在最小时间内被发送到I缓存，优选地只有当它已经被取出到该行并且没有被无效时，因为哪个请求包括要被无效的地址，该标签和一个指示 线路用于PSC操作。 该方法还包括将请求地址与预取指令的存储地址进行比较，并且响应于匹配，在最大时间量内向LSU发送匹配指示符和标签。 匹配指示符相对于独占数据返回是定时的，使得LSU可以执行存储操作之后丢弃预取指令，存储到受独占数据返回的行，并且指示匹配。
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公开(公告)号：US07793086B2
公开(公告)日：2010-09-07
申请号：US11852443
申请日：2007-09-10
申请人： Gregory W. Alexander
发明人： Gregory W. Alexander
IPC分类号： G06F11/28
CPC分类号： G06F9/4486
摘要： A method for link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structures forming a common pool and an operation control table. Maintaining, within the common pool, a plurality of entries for a plurality of speculative instructions and a plurality of non-speculative instructions. And determining one speculative instruction to be a bad prediction speculative entry, identifying related entries to form a collection, and discarding the collection.
摘要翻译： 一种使用重命名结构链接堆栈错误预测分辨率的方法，用于跟踪链接堆栈处理，以便从错误预测的函数返回中快速解决链接堆栈损坏。 该方法包括建立一组形成公共池的物理数据结构和操作控制表。 在公共池内维护多个投机指令和多个非投机指令的多个条目。 并确定一个推测性指令是不良预测推测条目，识别相关条目以形成集合，并丢弃收集。
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7.发明授权公开(公告)号：US07769984B2
公开(公告)日：2010-08-03
申请号：US12208683
申请日：2008-09-11
CPC分类号： G06F9/3838
摘要： A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
摘要翻译： 解码双发指令以确定双发指令的LSU部分所需的多个LSU依赖性以及双发指令的非LSU部分所需的多个非LSU依赖性。 在由微处理器发出双发指令的情况下，双依赖矩阵采用如下方式：加载存储单元（LSU）依赖矩阵用多个LSU依赖性写入，非LSU依赖矩阵用 多个非LSU依赖关系; LSU问题有效（LSU IV）指标设置为有效发行; 一旦满足双重发出指令的多个LSU依赖性，就发出双发指令的LSU部分; 非LSU问题有效（非LSU IV）指标被设置为有效发行; 一旦满足双重发出指令的多个非LSU依赖关系，就发出双发指令的非LSU部分。 然后可以通知LSU依赖矩阵和非LSU依赖矩阵，使得依赖于双重发出指令的一个或多个指令现在可以被发布。
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8.发明授权公开(公告)号：US07645532B2
公开(公告)日：2010-01-12
申请号：US10909577
申请日：2004-08-02
CPC分类号： H01M8/0618 , C01B3/386 , C01B2203/0261 , C01B2203/066 , C01B2203/1288 , C01B2203/1604 , H01M8/04022 , H01M8/04134 , H01M2008/1293
摘要： A solid-oxide fuel cell system wherein a reformate combustor is disposed in the reformate flow path between a hydrocarbon reformer and a fuel cell stack. At system start-up, reformate is partially burned within the combustor by admitting combustion air, and the partially-burned reformate is passed through the anode chambers of the stack to warm the anodes. In addition, reformate is passed through a cathode-air heat exchanger to warm combustion air entering the cathode chambers of the stack. The combustor may continue to be supplied with a low level of air during steady-state operation of the SOFC, thereby providing a moist environment within the anode chambers to prevent coking of the anodes and providing additional heat to the reformate. The combustor decouples the reformer from the stack thermodynamically, permitting the reformer and the stack each to run in its own optimal temperature range.
摘要翻译： 一种固体氧化物燃料电池系统，其中重整燃烧器设置在烃重整器和燃料电池堆之间的重整产品流路中。 在系统启动时，通过加入燃烧空气在燃烧室内部分燃烧重整产物，部分燃烧的重整产物通过堆叠的阳极室，以加热阳极。 此外，重整产物通过阴极 - 空气热交换器以加热进入堆叠的阴极室的燃烧空气。 在SOFC的稳态操作期间，燃烧器可以继续供应低水平的空气，从而在阳极室内提供潮湿环境，以防止阳极焦化并向重整产品提供额外的热量。 燃烧器使热重分离器与热堆动力学解耦，允许重整器和堆叠各自运行在其最佳温度范围内。
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9.发明申请METHOD FOR SERIALIZING TRANSLATION LOOKASIDE BUFFER ACCESS AROUND ADDRESS TRANSLATION PARAMETER MODIFICATION 有权串行翻译查询缓冲区访问方法地址转换参数修改方法公开(公告)号：US20090210650A1
公开(公告)日：2009-08-20
申请号：US12032178
申请日：2008-02-15
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , G06F2212/684
摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.
摘要翻译： 本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。 提供处理器和计算机程序产品。
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10.发明授权Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions 有权从计数器池分配计数器，以跟踪逻辑寄存器到物理寄存器的映射，用于基于映射器的指令执行公开(公告)号：US08661230B2
公开(公告)日：2014-02-25
申请号：US13088298
申请日：2011-04-15
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/384
摘要： A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译： 无序处理器的映射器单元分配当前在计数器可用池中的特定计数器，以响应于由多个物理寄存器执行的指令来计数多个物理寄存器中的逻辑寄存器到多个物理寄存器的数量的映射 映射器单元将至少一个逻辑寄存器映射到特定物理寄存器。 计数器的数量少于物理寄存器的数量。 映射器单元响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。
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