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    Triggering workaround capabilities based on events active in a processor pipeline
    5.
    发明授权
    Triggering workaround capabilities based on events active in a processor pipeline 有权
    根据处理器管道中活动的事件触发解决方法的功能

    公开(公告)号：US08082467B2

    公开(公告)日：2011-12-20

    申请号：US12645771

    申请日：2009-12-23

    申请人： Gregory W. Alexander ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

    发明人： Gregory W. Alexander ,  Fadi Busaba ,  David A. Schroter ,  Eric Schwarz ,  Brian W. Thompto ,  Wesley J. Ward, III

    IPC分类号： G06F11/00

    CPC分类号： G06F9/30145 ,  G06F9/30189 ,  G06F9/3853 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/004 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/0793

    摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.

    摘要翻译： 公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。 从存储器位置获取至少一个指令。 该指令被解码。 与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。 响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。 该指令用基于操作码比较操作的模式标记。 该模式表示该指令与处理缺陷相关联。 该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

    Error detection enhancement in a microprocessor through the use of a second dependency matrix
    7.
    发明授权
    Error detection enhancement in a microprocessor through the use of a second dependency matrix 失效
    微处理器通过使用第二个依赖矩阵进行错误检测增强

    公开(公告)号：US07549095B1

    公开(公告)日：2009-06-16

    申请号：US12165355

    申请日：2008-06-30

    申请人： Gregory W. Alexander ,  Lee E. Eisen ,  Brian W. Thompto ,  John W. Ward, III

    发明人： Gregory W. Alexander ,  Lee E. Eisen ,  Brian W. Thompto ,  John W. Ward, III

    IPC分类号： H03M13/00

    CPC分类号： G06F9/3859 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3861 ,  G06F11/0721 ,  G06F11/0751

    摘要： A microprocessor error detection method, includes providing a primary dependency matrix, providing an issue logic for issuing a micro-op, providing a secondary dependency matrix comprising a copy of the primary dependency matrix, providing a results available vector, the results available vector including an entry for each dependency tracked, receiving an indication from issue logic that it is issuing a micro-op, reading the secondary dependency matrix row corresponding to the issued micro-op, checking if the micro-op being read is dependent on a tracked dependency that is not satisfied by determining if any bit set in the row read from the secondary dependency matrix is not set in the secondary results available vector, and receiving an indication from the issue logic if the micro-op has been rescinded.

    摘要翻译： 一种微处理器错误检测方法，包括提供主依赖矩阵，提供用于发布微操作的问题逻辑，提供包括主依赖矩阵的副本的辅依赖矩阵，提供结果可用向量，所述结果可用向量包括 接收跟踪的每个依赖关系的条目，从发出逻辑发出微操作的指示，读取对应于所发出的微操作的次要依赖矩阵行，检查所读取的微操作是否依赖于跟踪依赖性 通过确定从辅助依赖矩阵中读取的行中设置的任何位是否未被设置在辅助结果可用向量中，并且如果微操作被取消，则从发布逻辑接收指示。

    DYNAMIC RECALCULATION OF RESOURCE VECTOR AT ISSUE QUEUE FOR STEERING OF DEPENDENT INSTRUCTIONS
    8.
    发明申请
    DYNAMIC RECALCULATION OF RESOURCE VECTOR AT ISSUE QUEUE FOR STEERING OF DEPENDENT INSTRUCTIONS 有权
    发布问题动态资源向量的动态调整，用于指导相关指示

    公开(公告)号：US20080133890A1

    公开(公告)日：2008-06-05

    申请号：US12013572

    申请日：2008-01-14

    申请人： Hung Q. Le ,  Dung Q. Nguyen ,  Brian W. Thompto ,  Raymond C. Yeung

    发明人： Hung Q. Le ,  Dung Q. Nguyen ,  Brian W. Thompto ,  Raymond C. Yeung

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3851 ,  G06F9/3836

    摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.

    摘要翻译： 一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。 在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。 分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

    Management of multiple nested transactions
    9.
    发明授权
    Management of multiple nested transactions 有权
    管理多个嵌套事务

    公开(公告)号：US09298469B2

    公开(公告)日：2016-03-29

    申请号：US13524330

    申请日：2012-06-15

    申请人： Fadi Y. Busaba ,  Brian W. Thompto

    发明人： Fadi Y. Busaba ,  Brian W. Thompto

    IPC分类号： G06F9/44 ,  G06F9/46 ,  G06F9/50 ,  G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/44 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/3857 ,  G06F9/466 ,  G06F9/467 ,  G06F9/50 ,  G06F9/5011 ,  G06F2209/507

    摘要： Embodiments relate to implementing processor management of transactions. An aspect includes receiving an instruction from a thread. The instruction includes an instruction type, and executes within a transaction. The transaction effectively delays committing stores to memory until the transaction has completed. A processor manages transaction nesting for the instruction based on the instruction type of the instruction. The transaction nesting includes a maximum processor capacity. The transaction nesting management performs enables executing a sequence of nested transactions within a transaction, supports multiple nested transactions in a processor pipeline, or generates and maintains a set of effective controls for controlling a pipeline. The processor prevents the transaction nesting from exceeding the maximum processor capacity.

    摘要翻译： 实施例涉及实现事务的处理器管理。 一方面包括从线程接收指令。 指令包括指令类型，并在事务中执行。 交易有效延迟提交存储到内存，直到交易完成。 处理器根据指令的指令类型管理指令的事务嵌套。 事务嵌套包括最大处理器容量。 事务嵌套管理执行使得能够在事务中执行嵌套事务序列，在处理器流水线中支持多个嵌套事务，或生成并维护一组用于控制流水线的有效控制。 处理器防止事务嵌套超出最大处理器容量。

    MANAGEMENT OF MULTIPLE NESTED TRANSACTIONS
    10.
    发明申请
    MANAGEMENT OF MULTIPLE NESTED TRANSACTIONS 有权
    多项交易的管理

    公开(公告)号：US20130339688A1

    公开(公告)日：2013-12-19

    申请号：US13524330

    申请日：2012-06-15

    申请人： Fadi Y. Busaba ,  Brian W. Thompto

    发明人： Fadi Y. Busaba ,  Brian W. Thompto

    IPC分类号： G06F9/38

    CPC分类号： G06F9/44 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/30145 ,  G06F9/3857 ,  G06F9/466 ,  G06F9/467 ,  G06F9/50 ,  G06F9/5011 ,  G06F2209/507

    摘要： Embodiments relate to implementing processor management of transactions. An aspect includes receiving an instruction from a thread. The instruction includes an instruction type, and executes within a transaction. The transaction effectively delays committing stores to memory until the transaction has completed. A processor manages transaction nesting for the instruction based on the instruction type of the instruction. The transaction nesting includes a maximum processor capacity. The transaction nesting management performs enables executing a sequence of nested transactions within a transaction, supports multiple nested transactions in a processor pipeline, or generates and maintains a set of effective controls for controlling a pipeline. The processor prevents the transaction nesting from exceeding the maximum processor capacity.

    摘要翻译： 实施例涉及实现事务的处理器管理。 一方面包括从线程接收指令。 指令包括指令类型，并在事务中执行。 交易有效延迟提交存储到内存，直到交易完成。 处理器根据指令的指令类型管理指令的事务嵌套。 事务嵌套包括最大处理器容量。 事务嵌套管理执行使得能够在事务中执行嵌套事务序列，在处理器流水线中支持多个嵌套事务，或生成并维护一组用于控制流水线的有效控制。 处理器防止事务嵌套超出最大处理器容量。