公开(公告)号：US06694344B1

公开(公告)日：2004-02-17

申请号：US09436851

申请日：1999-11-09

申请人： Guenter Gerwig ,  Juergen Haess ,  Michael Kroener ,  Erwin Pfeffer

发明人： Guenter Gerwig ,  Juergen Haess ,  Michael Kroener ,  Erwin Pfeffer

IPC分类号： G06F1100

CPC分类号： G06F11/085 ,  G06F7/72 ,  H03M7/02

摘要： A process is provided for monitoring the conversion of numerical values from a first to a second format, where before and after the conversion, the modulo residue of the corresponding numerical value is calculated and compared with the corresponding residue after the conversion. In this way it is possible to effect error-free monitoring of such a conversion, especially of computer data, without great hardware expenditure.

摘要翻译： 提供了用于监视从第一格式到第二格式的数值的转换的过程，其中在转换之前和之后，计算相应数值的模余数并将其与转换后的相应残差进行比较。 以这种方式，可以在没有很好的硬件支出的情况下，对这种转换，特别是计算机数据进行无差错监视。

公开(公告)号：US20060179100A1

公开(公告)日：2006-08-10

申请号：US11054686

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Lawrence Powell ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Lawrence Powell ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

IPC分类号： G06F7/38

CPC分类号： G06F9/3826 ,  G06F9/30014 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3885

摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.

摘要翻译： 一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。 该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。 该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。 这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在 存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。 此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作 在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

公开(公告)号：US07730117B2

公开(公告)日：2010-06-01

申请号：US11054110

申请日：2005-02-09

申请人： Bruce M. Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin S. Schmookler ,  Eric M. Schwarz ,  Son Dao-Trong

发明人： Bruce M. Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin S. Schmookler ,  Eric M. Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38 ,  G06F15/00

CPC分类号： G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。 该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US07188233B2

公开(公告)日：2007-03-06

申请号：US11054686

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Quoc Nguyen ,  Lawrence J. Powell, Jr. ,  Eric M. Schwarz ,  Son Dao-Trong ,  Raymond C. Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Quoc Nguyen ,  Lawrence J. Powell, Jr. ,  Eric M. Schwarz ,  Son Dao-Trong ,  Raymond C. Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/3826 ,  G06F9/30014 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3885

摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.

摘要翻译： 一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。 该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。 该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。 这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在 存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。 此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作 在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

公开(公告)号：US20060179286A1

公开(公告)日：2006-08-10

申请号：US11054201

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Nguyen ,  Eric Schwarz ,  Son Dao-Trong ,  Raymond Yeung

IPC分类号： G06F9/44

CPC分类号： G06F9/3867 ,  G06F9/3838

摘要： A system for performing limited out-of order execution of floating point loads. The system includes a plurality of stages making up a pipeline, the stages including an early stage. The system also includes a mechanism for inputting an arithmetic instruction into the pipeline, the arithmetic instruction including a result address. The mechanism also determines if the arithmetic instruction causes a write after write (WAW) condition to occur before writing a result of the arithmetic instruction to the result address. The determining includes comparing the result address to a load address associated with a load instruction subsequent to the arithmetic instruction in the pipeline. The load data associated with the load instruction was written to the load address in the early stage of the pipeline. A WAW condition occurs if the result address is equal to the load address. Writing a result of the arithmetic instruction is suppressed in response to the WAW condition occurring.

摘要翻译： 用于执行浮点负载有限次序执行的系统。 该系统包括构成管道的多个阶段，这些阶段包括早期阶段。 该系统还包括用于将算术指令输入流水线的机构，算术指令包括结果地址。 该机制还确定在将算术指令的结果写入结果地址之前，算术指令是否在写入（WAW）条件之后发生写入。 确定包括将结果地址与在流水线中的算术指令之后的加载指令相关联的加载地址进行比较。 与加载指令相关联的加载数据在管道的早期阶段被写入加载地址。 如果结果地址等于加载地址，则会发生WAW条件。 响应于发生的WAW状态，写入算术指令的结果被抑制。

公开(公告)号：US20060179097A1

公开(公告)日：2006-08-10

申请号：US11054110

申请日：2005-02-09

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/499 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/5443 ,  G06F2207/382

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。 该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US20060179096A1

公开(公告)日：2006-08-10

申请号：US11055232

申请日：2005-02-10

申请人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

发明人： Bruce Fleischer ,  Juergen Haess ,  Michael Kroener ,  Robert Montoye ,  Martin Schmookler ,  Eric Schwarz ,  Son Dao-Trong

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F7/49947 ,  G06F7/5443

摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes computer instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.

摘要翻译： 一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。 该系统还包括用于响应于确定操作数是单精度来执行操作数的单精度递增的计算机指令，操作数基于先前操作的结果需要增加，并且先前的操作未执行递增。 操作数是在以前的操作中创建的。 该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

公开(公告)号：US08346828B2

公开(公告)日：2013-01-01

申请号：US12250935

申请日：2008-10-14

申请人： Maarten Boersma ,  Michael Kroener ,  Petra Leber ,  Silvia M. Mueller ,  Jochen Preiss ,  Kerstin Schelm

发明人： Maarten Boersma ,  Michael Kroener ,  Petra Leber ,  Silvia M. Mueller ,  Jochen Preiss ,  Kerstin Schelm

IPC分类号： G06F5/00

CPC分类号： G06F9/30025 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30192 ,  G06F2207/3824

摘要： A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.

摘要翻译： 提供了一种用于将数字存储在寄存器文件中的系统和方法。 系统和方法以浮点数计算单位和不支持浮点数的计算单位共享的寄存器文件中存储双精度格式的单精度数字。

公开(公告)号：US20110320512A1

公开(公告)日：2011-12-29

申请号：US12821648

申请日：2010-06-23

申请人： Steven R. Carlough ,  Adam B. Collura ,  Michael Kroener ,  Silvia Melitta Mueller

发明人： Steven R. Carlough ,  Adam B. Collura ,  Michael Kroener ,  Silvia Melitta Mueller

IPC分类号： G06F7/44 ,  G06F5/01

CPC分类号： G06F7/4915 ,  G06F2207/4911

摘要： A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format.

摘要翻译： 具有系数机制而不产生前导零检测（LZD）的计算机中的固定和浮点计算的十进制乘法机制，其假设最终产品的长度为M + N个数字，并且基于该假设执行所有计算。 将被截断的最低有效数字不再存储，而是保留为用于确定结果产品的粘性信息。 一旦产品的计算完成，就使用基于在部分积累期间观察到的关键位的检查的最终检查来确定最终产品是真正的M + N个数字的长度，还是M + N-1个数字。 如果后者是真实的，则采用校正最终产品转换来获得适当的结果。 这消除了用于确定最终产品中有效数字数量的专用前导零检测硬件的需要。 当产品的指数处于极端状态并且最终产品必须在给定格式的精度和范围内时，纠正性最终产品转移也会对产品系数进行调整。

公开(公告)号：US08032854B2

公开(公告)日：2011-10-04

申请号：US12201092

申请日：2008-08-29

申请人： Maarten Boersma ,  Michael Kroener ,  Petra Leber ,  Silvia M. Mueller ,  Jochen Preiss ,  Kerstin Schelm

发明人： Maarten Boersma ,  Michael Kroener ,  Petra Leber ,  Silvia M. Mueller ,  Jochen Preiss ,  Kerstin Schelm

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.

摘要翻译： 用于浮点单元的三层平面布置图包括：位于浮点单元中心的对准器; 位于对准器正上方的前端; 位于前端正对着对准器旁边的乘数; 位于乘法器旁边并直接位于校准器下方的加法器; 位于加法器正上方的归一化器; 以及位于归一化器正上方的四舍五入。