公开(公告)号：US07188233B2

公开(公告)日：2007-03-06

申请号：US11054686

申请日：2005-02-09

申请人： Juergen Haess ,  Michael Kroener ,  Dung Quoc Nguyen ,  Lawrence J. Powell, Jr. ,  Eric M. Schwarz ,  Son Dao-Trong ,  Raymond C. Yeung

发明人： Juergen Haess ,  Michael Kroener ,  Dung Quoc Nguyen ,  Lawrence J. Powell, Jr. ,  Eric M. Schwarz ,  Son Dao-Trong ,  Raymond C. Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/3826 ,  G06F9/30014 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3885

摘要： A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.

摘要翻译： 一种用于执行浮点算术运算的系统，包括构成流水线的多个级，所述级包括第一级和最后级。 该系统还包括适于接收用于输入到流水线的存储指令的寄存器文件，其中与存储指令相关联的数据依赖于仍在流水线中的先前操作。 该系统还包括适于将与存储指令相关联的数据输出到存储器的存储寄存器和具有指令的控制单元。 这些指令旨在将存储指令输入到流水线中，并且提供一个路径，用于将与流水线中的最后一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用，如果先前的操作紧接在 存储操作在流水线中，并且存储指令与先前操作之间存在数据类型匹配。 此外，该指令旨在将存储指令输入到流水线中，并且提供用于将与流水线中的第一级相关联的存储指令的数据转发到存储寄存器以供存储指令使用的路径，如果先前的操作 在存储操作之前在流水线中的一个或多个阶段，以及存储指令和先前操作之间是否存在数据类型匹配。

公开(公告)号：US08418180B2

公开(公告)日：2013-04-09

申请号：US12129876

申请日：2008-05-30

申请人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： James Wilson Bishop ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/46

CPC分类号： G06F9/30101 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4818 ,  G06F9/485

摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.

摘要翻译： 公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。 在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。 如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。 超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。 响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

公开(公告)号：US07663963B2

公开(公告)日：2010-02-16

申请号：US12134537

申请日：2008-06-06

申请人： Sam Gat-Shang Chu ,  Maureen Anne Delaney ,  Saiful Islam ,  Dung Quoc Nguyen ,  Jafar Nahidi

发明人： Sam Gat-Shang Chu ,  Maureen Anne Delaney ,  Saiful Islam ,  Dung Quoc Nguyen ,  Jafar Nahidi

IPC分类号： G11C8/00

CPC分类号： G06F9/30141

摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。

公开(公告)号：US20090063898A1

公开(公告)日：2009-03-05

申请号：US12270300

申请日：2008-11-13

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/20

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US07490226B2

公开(公告)日：2009-02-10

申请号：US11054289

申请日：2005-02-09

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F9/312

CPC分类号： G06F9/383 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3867

摘要： A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includes the step of issuing a first instruction, such as an FMA instruction, to move through the sequence of execution stages, the first instruction being directed to a specified one of the registers. The method further includes issuing a second instruction to move through the execution stages, the second instruction being issued after the first instruction has issued, but before the first instruction reaches the final write back stage. The second instruction is likewise directed to the specified register, and comprises either a store instruction or a load instruction, selectively. R and W bits corresponding to the specified register are used to ensure that a store instruction does not read data from, and that a load instruction does not write data to the specified register, respectively, before the first instruction is moved to the final write back stage.

摘要翻译： 提供了一种用于具有多个寄存器的处理器的方法和相关装置，其中顺序地发出指令以从初始阶段到最终回写阶段移动经过一系列执行阶段。 作为一种方法，实施例包括发出诸如FMA指令的第一指令以移动经过执行级序列的步骤，第一指令被引导到指定的一个寄存器。 该方法还包括发出第二指令以移动通过执行阶段，第二指令在第一指令发出之后但在第一指令到达最终回写阶段之前发出。 第二条指令同样针对指定的寄存器，并且选择性地包括存储指令或加载指令。 使用与指定寄存器相对应的R和W位来确保存储指令不会从第一指令移动到最终回写之前分别读取数据，并且加载指令不会将数据写入指定的寄存器 阶段。

公开(公告)号：US07467325B2

公开(公告)日：2008-12-16

申请号：US11055258

申请日：2005-02-10

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/00

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US20080222395A1

公开(公告)日：2008-09-11

申请号：US11683843

申请日：2007-03-08

申请人： Hung Qui Le ,  Dung Quoc Nguyen

发明人： Hung Qui Le ,  Dung Quoc Nguyen

IPC分类号： G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3857 ,  G06F9/3859

摘要： A system and method for predictive early allocation of stores in a microprocessor is presented. During instruction dispatch, an instruction dispatch unit retrieves an instruction from an instruction cache (Icache). When the retrieved instruction is an interruptible instruction, the instruction dispatch unit loads the interruptible instruction's instruction tag (IITAG) into an interruptible instruction tag register. A load store unit loads subsequent instruction information (instruction tag and store data) along with the interruptible instruction tag in a store data queue entry. Comparison logic receives a completing instruction tag from completion logic, and compares the completing instruction tag with the interruptible instruction tags included in the store data queue entries. In turn, deallocation logic deallocates those store data queue entries that include an interruptible instruction tag that matches the completing instruction tag.

摘要翻译： 提出了一种用于在微处理器中预先提前存储分配的系统和方法。 在指令调度期间，指令调度单元从指令高速缓存（Icache）检索指令。 当检索到的指令是可中断指令时，指令调度单元将可中断指令的指令标记（IITAG）加载到可中断指令标记寄存器中。 加载存储单元将后续指令信息（指令标签和存储数据）与可中断指令标签一起存储在存储数据队列条目中。 比较逻辑从完成逻辑接收完成指令标记，并将完成指令标签与包含在存储数据队列条目中的可中断指令标签进行比较。 反过来，解配分配逻辑会释放那些包含与完成指令标记匹配的可中断指令标签的存储数据队列条目。

公开(公告)号：US07000047B2

公开(公告)日：2006-02-14

申请号：US10422036

申请日：2003-04-23

申请人： Dung Quoc Nguyen ,  Raymond Cheung Yeung

发明人： Dung Quoc Nguyen ,  Raymond Cheung Yeung

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F15/16 ,  G06F9/46

CPC分类号： G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A method and multithreaded processor for handling livelocks in a simultaneous multithreaded processor. A number of instructions for a thread in a queue may be counted. A counter in the queue may be incremented if the number of instructions for the thread in the queue in a previous clock cycle is equal to the number of instructions for the thread in the queue in a current clock cycle. If the value of the counter equals a threshold value, then a livelock condition may be detected. Further, if the value of the counter equals a threshold value, a recovery action may be activated to handle the livelock condition detected. The recovery action may include blocking the instructions associated with a thread causing the livelock condition from being executed thereby ensuring that the locked thread makes forward progress.

摘要翻译： 一种用于处理同时多线程处理器中的活动锁的方法和多线程处理器。 可以对队列中的线程的许多指令进行计数。 如果先前时钟周期中队列中的线程的指令数目等于当前时钟周期中队列中线程的指令数，队列中的计数器可能会增加。 如果计数器的值等于阈值，则可以检测到活动锁定状态。 此外，如果计数器的值等于阈值，则可以激活恢复动作来处理检测到的活动锁定状态。 恢复动作可以包括阻止与线程相关联的指令，导致活动锁定条件被执行，从而确保锁定的线程前进进行。

公开(公告)号：US06826678B2

公开(公告)日：2004-11-30

申请号：US10122034

申请日：2002-04-11

申请人： Hung Qui Le ,  Dung Quoc Nguyen

发明人： Hung Qui Le ,  Dung Quoc Nguyen

IPC分类号： G06F938

CPC分类号： G06F9/3867 ,  G06F9/3836 ,  G06F9/384

摘要： A method, processor architecture, computer program product, and data processing system for determining when an instruction in a pipelined processor should be completed is provided. As each instruction is issued to an execution unit, an entry for that instruction is placed within a “finish pipe,” which consists of a series of consecutively numbered stages. Each clock cycle, the entries in the finish pipe advance one stage. When an entry has reached the stage corresponding to the latency of its associated execution unit, it becomes mature. Each clock cycle, the finish pipe is scanned to find the entry having the highest-numbered stage of any entry in the finish pipe. If that entry is mature, it is removed from the finish pipe and the instructions associated with that entry is allowed to complete. If not, the entry simply advances along with the other entries and the pipe rescanned in the next cycle.

摘要翻译： 提供了一种用于确定何时应该完成流水线处理器中的指令的方法，处理器架构，计算机程序产品和数据处理系统。 当每个指令被发送到执行单元时，该指令的条目被放置在由“连续编号”序列组成的“完成管道”内。 每个时钟周期，完成管道中的条目提前一个阶段。 当条目达到与其关联的执行单元的延迟对应的阶段时，它变得成熟。每个时钟周期，扫描完成管道以找到完成管道中任何条目的最高编号阶段的条目。 如果该条目成熟，将从完成管道中删除，并允许与该条目关联的指令完成。 如果没有，则条目将随着其他条目和下一个循环中重新扫描的管道而前进。

公开(公告)号：US06535973B1

公开(公告)日：2003-03-18

申请号：US09383606

申请日：1999-08-26

申请人： Hoichi Cheong ,  Maureen A. Delaney ,  Hung Qui Le ,  Robert McDonald ,  Dung Quoc Nguyen ,  David Wayne Victor

发明人： Hoichi Cheong ,  Maureen A. Delaney ,  Hung Qui Le ,  Robert McDonald ,  Dung Quoc Nguyen ,  David Wayne Victor

IPC分类号： G06F9312

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384

摘要： A method and system for speculatively issuing instructions which are dependent upon results from execution of other instructions. Instructions are speculatively issued, dependent upon a result from execution of a primary instruction, wherein the speculatively issued instructions are issued after execution of the primary instruction. N clock cycles are tracked after execution of the primary instruction, wherein the result from execution of said primary instruction is expected within n clock cycles. Execution of any speculatively issued instructions which are dependent upon the primary instruction is cancelled if the result is not returned from execution of the primary instruction within n clock cycles, such that for primary instructions for which the result is returned within the expected n clock cycles any speculatively issued instructions dependent upon said result are executed with increased efficiency.

摘要翻译： 用于推测发出指令的方法和系统，其依赖于执行其他指令的结果。 根据执行主指令的结果推测发出指令，其中在执行主指令之后发出推测发出的指令。 在执行主指令之后追踪N个时钟周期，其中预期在n个时钟周期内执行所述主指令的结果。 如果在n个时钟周期内没有从主指令的执行中返回结果，则取消依赖于主指令的任何推测发出的指令的执行，使得对于在预期的n个时钟周期内返回结果的主指令， 推测发出依赖于所述结果的指令以更高的效率执行。