利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

106 条记录 (耗时 0.027 秒)

    Matched filter circuit for spread spectrum communication
    4.
    发明授权
    Matched filter circuit for spread spectrum communication 失效
    用于扩频通信的匹配滤波电路

    公开(公告)号：US06031415A

    公开(公告)日：2000-02-29

    申请号：US733820

    申请日：1996-10-18

    申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

    发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

    IPC分类号： H04J13/00 ,  H03H17/02 ,  H04B1/7093 ,  H03K5/00 ,  H03D1/00

    CPC分类号： H03H17/0254 ,  H04B1/707

    摘要： The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

    摘要翻译： 本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。 根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。

    Matched filter circuit
    5.
    发明授权
    Matched filter circuit 失效
    匹配滤波电路

    公开(公告)号：US5926512A

    公开(公告)日：1999-07-20

    申请号：US735787

    申请日：1996-10-23

    申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

    发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

    IPC分类号： H04J13/00 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H04B1/7093 ,  H03D1/00 ,  H04L27/06

    CPC分类号： H03H11/04 ,  H03H17/0254 ,  Y02B60/50

    摘要： A matched filter circuit for mobile communications is disclosed. The circuit may be fabricated in a small size using large-scale integration and can perform high-speed processing and double sampling at a reduced rate of power consumption. In one embodiment, a plurality of sampling and holding circuits each including a switch are divided into two groups. A control circuit successively closes one of the switches in the first group every chip time, while successively closing one of the switches in the second group at a timing shifted by one-half chip time from that of the first group, thereby enabling a double-sampling operation. Outputs of the sampling and holding circuits in each group are summed by an analog circuit with a high degree of linearity, resulting in a high processing speed combined with a reduced circuit size and power consumption.

    摘要翻译： 公开了一种用于移动通信的匹配滤波器电路。 该电路可以使用大规模集成在小尺寸上制造，并且可以以降低的功率消耗来执行高速处理和双重采样。 在一个实施例中，每个包括开关的多个采样和保持电路被分成两组。 控制电路在每个码片时间连续地闭合第一组中的一个开关，同时以与第一组相比半个码片时间偏移的时间顺序地关闭第二组中的一个开关，由此， 抽样操作。 每个组中的采样和保持电路的输出由具有高线性度的模拟电路相加，导致高处理速度以及减小的电路尺寸和功耗。

    Acquisition scheme and receiver for an asynchronous DS-CDMA cellular communication system
    6.
    发明授权
    Acquisition scheme and receiver for an asynchronous DS-CDMA cellular communication system 失效
    异步DS-CDMA蜂窝通信系统的采集方案和接收机

    公开(公告)号：US5910948A

    公开(公告)日：1999-06-08

    申请号：US955613

    申请日：1997-10-22

    申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

    发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

    IPC分类号： H04B1/707 ,  H04B1/708 ,  H04B1/7083 ,  H04B7/26 ,  H04J13/00 ,  H04L7/00 ,  H04W36/00 ,  H04W48/18 ,  H04W56/00 ,  H04B7/216

    CPC分类号： H04W48/18 ,  H04B1/70735 ,  H04B1/70775 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70702 ,  H04W36/00

    摘要： The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.

    摘要翻译： 本发明实现了用于异步DS-CDMA蜂窝系统的快速且有效的小区搜索和小尺寸仪器。 该小区搜索检测接收信号与控制信道的短码之间的相关性，匹配滤波器22检测最大功率相关峰位置。 接下来，使用多个并行设置为用于RAKE处理的多个的相关器28-1至28-n识别具有检测到的长码定时的系统中设置的长码。 在长代码同步之后，使用28-1至28-n接收多路径信号，并且通过RAKE处理来判断数据。 当执行外围小区搜索时，在通过使用匹配滤波器22检测长码定时之后，使用相同的匹配滤波器来指定候选周边小区的长码。 通过由相关器28-1至28-n接收来自所连接的基站的信号，以及通过22次切换的基站信号来安全地实现切换。

    Discrete cosine transformation circuit
    9.
    发明授权
    Discrete cosine transformation circuit 失效
    离散余弦变换电路

    公开(公告)号：US5862070A

    公开(公告)日：1999-01-19

    申请号：US820002

    申请日：1997-03-18

    申请人： Guoliang Shou ,  Jie Chen ,  Chanming Zhou ,  Sunao Takatori

    发明人： Guoliang Shou ,  Jie Chen ,  Chanming Zhou ,  Sunao Takatori

    IPC分类号： G06F17/14 ,  G06G7/22 ,  G06G7/02 ,  G06G7/19

    CPC分类号： G06G7/22 ,  G06F17/147

    摘要： A high-speed discrete cosine transformation circuit includes the one-dimensional input signals x(0) to x(7) being input in parallel to the positive input terminals "+" or the negative input terminals "-" of eight neural operation units (NOU) 11 to 18 through capacitors d0 to d6. In each NOU 11 to 18, input signals x(0) to x(7) are added and subtracted. Input signals x(0) to x(7) are multiplied beforehand by the coefficient in proportion to the capacities of capacitors d0 to d6 which are connected to NOU 11 to 18. Thereafter, discrete cosine transforming coefficients y(0) to y(7) are output. A two-dimensional discrete cosine transformation circuit is realized by using the one-dimensional discrete cosine transforming circuit.

    摘要翻译： 高速离散余弦变换电路包括与八个神经运算单元的正输入端子“+”或负输入端子“ - ”并联输入的一维输入信号x（0）〜x（7） NOU）11至18通过电容器d0至d6。 在每个NOU 11至18中，输入信号x（0）至x（7）被加和减。 输入信号x（0）至x（7）预先乘以与连接到NOU 11至18的电容器d0至d6的电容成比例的系数。之后，离散余弦变换系数y（0）至y（7 ）被输出。 通过使用一维离散余弦变换电路实现二维离散余弦变换电路。