公开(公告)号：US06343307B1

公开(公告)日：2002-01-29

申请号：US09277322

申请日：1999-03-26

申请人： David Mendlovic ,  Zeev Zalevsky ,  Gal Shabtay ,  Uriel Levy ,  Emanuel Marom ,  Naim Konforti

发明人： David Mendlovic ,  Zeev Zalevsky ,  Gal Shabtay ,  Uriel Levy ,  Emanuel Marom ,  Naim Konforti

IPC分类号： G06G702

CPC分类号： G06E1/00 ,  G02B5/20 ,  G02B27/42 ,  G02B27/4233 ,  G02B27/4266

摘要： A method and system for synthesizing a desired light beam including calculating a two-dimensional light filter for an optical element, the two-dimensional light filter being such that the optical element produces under free space propagation, in response to illumination thereof, a three-dimensional light distribution that approximates the light distribution of the desired light beam, and illuminating the optical element.

摘要翻译： 一种用于合成期望光束的方法和系统，包括计算用于光学元件的二维光滤波器，所述二维滤光器使得光学元件响应于其照明而在自由空间传播下产生三维滤光器， 近似于期望光束的光分布并且照射光学元件的三维光分布。

公开(公告)号：US06408322B1

公开(公告)日：2002-06-18

申请号：US09251670

申请日：1999-02-17

申请人： David Lowell McNeely

发明人： David Lowell McNeely

IPC分类号： G06G702

CPC分类号： H03H17/0288 ,  H03H17/0223

摘要： The disclosed filter structure employs parallel first and second input signal data paths. The first data path includes a digital Finite Impulse Response (FIR) filter having a small number of non-zero multiplier coefficients to define its theoretical impulse frequency response. The second data path includes plural series filters including (1) a digital FIR or Infinite Impulse Response (IIR) filter including a reduced-number of designer-chosen non-zero multiplier coefficients that tend to introduce error sources in the physical-realized filter structure's impulse frequency response and (2) a set of one or more frequency stop filters, each of which permits zero signal transmission therethrough at a different selected frequency. This arrangement anchors the frequency response value of the filter structure near each of the different selected frequencies of the set substantially at the corresponding theoretical impulse frequency response value of the digital FIR filter of the first data path near that one of the plurality of different selected frequencies of the set. The summed outputs of the first and second data paths is the filter output.

摘要翻译： 所公开的滤波器结构采用并行的第一和第二输入信号数据路径。 第一数据路径包括具有少量非零乘数系数的数字有限脉冲响应（FIR）滤波器，以定义其理论脉冲频率响应。 第二数据路径包括多个串联滤波器，包括（1）数字FIR或无限脉冲响应（IIR）滤波器，其包括减少数量的设计者选择的非零乘数系数，其倾向于在物理实现的滤波器结构的 脉冲频率响应和（2）一组一个或多个频率停止滤波器，其中每个滤波器允许以不同的选定频率通过其中的零信号传输。 这种布置基本上在第一数据路径的数字FIR滤波器的相应的理论脉冲频率响应值附近，将滤波器结构的频率响应值定位在该组的不同选定频率附近，该频率响应值靠近该多个不同选定频率 的集合。 第一和第二数据路径的相加输出是滤波器输出。

公开(公告)号：US06266689B1

公开(公告)日：2001-07-24

申请号：US09105200

申请日：1998-06-26

申请人： Thorsten Shier ,  Svante Signell

发明人： Thorsten Shier ,  Svante Signell

IPC分类号： G06G702

CPC分类号： H03H19/004

摘要： A complex switched capacitor filter is formed by selecting an analog baseband prototype filter with the desired filter characteristics. This prototype is converted into a corresponding real switched capacitor filter, and finally the real switched capacitor filter is converted into a complex switched capacitor filter by replacing each element of real filter by a frequency shifted complex counterpart.

摘要翻译： 通过选择具有所需滤波器特性的模拟基带原型滤波器来形成复合开关电容滤波器。 该原型被转换成相应的实际开关电容滤波器，最后通过将频率移位复数对应物替换为实际滤波器的每个元件，将实际开关电容滤波器转换为复合开关电容滤波器。

公开(公告)号：US06389445B1

公开(公告)日：2002-05-14

申请号：US09358293

申请日：1999-07-21

申请人： Yannis Tsividis

发明人： Yannis Tsividis

IPC分类号： G06G702

CPC分类号： G06K9/00503

摘要： Electrical filter or signal processor circuits are provided with internal companding for reduced sensitivity to noise while input-output response is as conventionally specified. In the continuous-time case, for a specified circuit described by state equations with a state vector x(t), state equations are derived of an equivalent companding circuit having a state vector w(t)=G(t)x(t), where G(t) is a suitably chosen matrix. G(t) may be chosen for instantaneous or syllabic companding of the state vector. A corresponding technique applies to discrete-time circuits.

摘要翻译： 电气滤波器或信号处理器电路具有内部压扩功能，以降低对噪声的灵敏度，而输入 - 输出响应是常规规定的。 在连续时间情况下，对于由具有状态向量x（t）的状态方程描述的指定电路，导出具有状态向量w（t）= G（t）x（t）的等效压扩电路的状态方程， ，其中G（t）是适当选择的矩阵。 可以选择G（t）用于状态向量的瞬时或音节压扩。 相应的技术适用于离散时间电路。

公开(公告)号：US06237017B1

公开(公告)日：2001-05-22

申请号：US08638071

申请日：1996-04-25

申请人： Vinod Menezes

发明人： Vinod Menezes

IPC分类号： G06G702

CPC分类号： G06J1/00

摘要： The present invention includes a data compression system which implements transformation and quantization functions using analog devites. The system includes a transformation module with analog devices (22), a quantization module with analog devices (24) and an entropy coding module (26). A data decompression system which implements inverse transformation and inverse quantization functions using analog devices is also shown.

摘要翻译： 本发明包括使用模拟视频实现变换和量化功能的数据压缩系统。 该系统包括具有模拟设备（22），具有模拟设备（24）的量化模块和熵编码模块（26）的变换模块。 还示出了使用模拟设备实现逆变换和逆量化功能的数据解压缩系统。

公开(公告)号：US06233598B1

公开(公告)日：2001-05-15

申请号：US09151433

申请日：1998-09-11

申请人： Robert Andrew Kertis

发明人： Robert Andrew Kertis

IPC分类号： G06G702

CPC分类号： G11B5/52

摘要： An interleaved finite impulse response (FIR) filter apparatus is provided for data detection in a direct access storage device. The FIR filter includes a plurality of sample and hold circuits. Each sample and hold circuit samples an input signal sequentially at a clock rate. At least one set of multiple multipliers is coupled to the plurality of sample and hold circuits. Each multiplier multiplies a sample by a predefined value and provides a multiplier product at the clock rate. At least a pair of summing functions are coupled to the set of multipliers. Each summing function adds a predetermined combination of respective multiplier products and provides at least a pair of interleave outputs. Each of the interleave outputs is provided at less than the clock rate.

摘要翻译： 提供交错式有限脉冲响应（FIR）滤波器装置用于直接存取存储装置中的数据检测。 FIR滤波器包括多个采样和保持电路。 每个采样和保持电路以时钟速率顺序采样输入信号。 至少一组多个乘法器耦合到多个采样和保持电路。 每个乘法器将样本乘以预定义值，并以时钟速率提供乘法器乘积。 至少一对求和函数耦合到该乘法器组。 每个求和函数添加各个乘法器乘积的预定组合并且提供至少一对交织输出。 每个交错输出以小于时钟速率提供。

公开(公告)号：US06216148B1

公开(公告)日：2001-04-10

申请号：US09191249

申请日：1998-11-12

申请人： Patrick J. Moran ,  Ivan Tin-Yam Chan ,  Ke Han

发明人： Patrick J. Moran ,  Ivan Tin-Yam Chan ,  Ke Han

IPC分类号： G06G702

CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B2020/10944

摘要： A single analog filter structure within a partial response channel combines an antialias low pass filter and a time domain waveform shaping equalizer upstream of a digital sampler. The filter also improves latencies associated with timing acquisition of a sampler clock generator loop by removing the latency of a separate equalization filter. The filter also provides a method for adapting a combination of internal filter state voltages and currents in real time for optimizing pole locations of the analog filter structure, during both data and timing recovery operations of the channel.

摘要翻译： 部分响应通道内的单个模拟滤波器结构将数字采样器上游的抗锯齿低通滤波器和时域波形整形均衡器相结合。 滤波器还通过消除单独的均衡滤波器的延迟来改进与采样器时钟发生器回路的定时采集相关的延迟。 滤波器还提供了一种用于在通道的数据和定时恢复操作期间实时地适配内部滤波器状态电压和电流的组合以优化模拟滤波器结构的极点位置的方法。

公开(公告)号：US06785622B2

公开(公告)日：2004-08-31

申请号：US10020673

申请日：2001-10-29

申请人： Richard A Nygaard, Jr.

发明人： Richard A Nygaard, Jr.

IPC分类号： G06G702

CPC分类号： H04L1/24

摘要： An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”). After watching a specified combination for the requisite length of time or number of events, the number of SUT clock cycles involved and the associated number of hits are stored in memory using a data structure indexed by the components of the specified combination (data signal delay, threshold). Next, a new combination of data signal delay and threshold is specified and a measurement taken and recorded in the data structure. The process is repeated until all possible combinations within a stated range of data signal delay and threshold voltage (using specified resolution/step sizes for delay and voltage) have been investigated. As this process proceeds under the control of firmware within the logic analyzer, other firmware can be examining the data structure and generating a partial eye diagram visible on a display, and that will be complete soon after the measurement itself is finished.

摘要翻译： 一个眼图分析仪为每个SUT数据和时钟信号输入通道在各自的路径中分别具有可变延迟。 对于n个许多SUT时钟周期的信号延迟范围，SUT时钟信号延迟可能设置在大约n / 2。 对于每个数据通道，指定相对于延迟的时钟信号（数据信号延迟）的实例和电压阈值的时间点。 指定的组合（数据信号延迟，阈值和哪个通道）是眼图上的位置，尽管迹线可能或不会经过该位置。 计数器对用作眼图参考实例的SUT时钟周期数进行计数，另一个计数器计算满足指定的条件组合的次数（“命中”）。 在所需时间长度或事件数量观察指定的组合之后，使用由指定组合的分量索引的数据结构（数据信号延迟， 阈）。 接下来，指定数据信号延迟和阈值的新组合，并在数据结构中进行测量并记录。 重复该过程，直到已经研究了所规定的数据信号延迟和阈值电压范围内的所有可能的组合（使用指定的分辨率/用于延迟和电压的步长）。 当该过程在逻辑分析仪内的固件的控制下进行时，其他固件可以检查数据结构并产生在显示器上可见的部分眼图，并且将在测量本身完成之后立即完成。

公开(公告)号：USRE37953E1

公开(公告)日：2002-12-31

申请号：US09404783

申请日：1999-09-24

申请人： Guoliang Shou ,  Chanming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

发明人： Guoliang Shou ,  Chanming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC分类号： G06G702

CPC分类号： H03H17/0254 ,  H03H11/04 ,  H04B1/7093

摘要： The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

摘要翻译： 本发明的目的是提供一种用于通信生成有效数字输出的滤波器电路以及低功耗滤波电路中的模拟输出。 根据通过在采集之后对信号进行部分采样可以执行峰值检测的经验，间歇地保持模拟输出信号，使A / D转换电路的功能速度最小化。

公开(公告)号：US06314444B1

公开(公告)日：2001-11-06

申请号：US09099724

申请日：1998-06-19

申请人： Vadim B. Minuhin ,  Bernardo Rub

发明人： Vadim B. Minuhin ,  Bernardo Rub

IPC分类号： G06G702

CPC分类号： H03H15/00

摘要： A second order filter-delay element for use in a generalized analog transversal equalizer is described which provides phase and group delay responses equivalent to low-pass filters of third and fourth order. In addition, the filter-delay element provides sufficient values of delays required for proper operations of the analog generalized transversal equalizer despite having a low order. In addition, a method of generating the lower order filter-delay element is described. Also, a circuit embodying an active C-transconductor realization of a second order filter-delay element for use in a generalized analog transversal equalizer with a transfer function designed as a result of performing the method is described.

摘要翻译： 描述了用于广义模拟横向均衡器中的二阶滤波器延迟元件，其提供等效于第三和第四级的低通滤波器的相位和组延迟响应。 此外，滤波器延迟元件提供足够的模拟广义横向均衡器的正确操作所需的延迟值，尽管具有低阶。 此外，描述了生成低阶滤波器延迟元件的方法。 此外，描述了一种实现用于具有作为执行该方法的结果设计的传递函数的广义模拟横向均衡器中的二阶滤波器延迟元件的有源C跨导体实现的电路。